ADUC7124 Analog Devices, ADUC7124 Datasheet - Page 39

• Manufacturer Part Number: ADUC7124
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7124

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 32000Bytes
• Gpio Pins: 30
• Adc # Channels: 12

Bit
[2:0]
ADCCP Register
Name:
Address:
Default Value:
Access:
ADCCP is an ADC positive channel selection register. This
MMR is described in Table 31.
Table 31. ADCCP
Bit
[7:5]
[4:0]
1
ADC and DAC channel availability depends on part model. See the Ordering
Guide for details.
Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
Others
Value
000
001
010
011
100
101
Other
1
Description
Reserved.
Positive channel selection bits.
ADC0.
ADC1.
ADC2.
ADC3.
ADC4.
ADC5.
ADC6.
ADC7.
ADC8.
ADC9.
ADC10.
ADC11.
DAC0/ADC12.
DAC1/ADC13.
DAC2/ADC14.
DAC3/ADC15.
Temperature sensor.
AGND (self-diagnostic feature).
Internal reference (self-diagnostic feature).
AV
Reserved.
Description
Conversion type.
Enable CONV
Enable Timer1 as a conversion input.
Enable Timer0 as a conversion input.
Single software conversion. Sets to 000 after
conversion (note that Bit 7 of ADCCON MMR
should be cleared after starting a single
software conversion to avoid further
conversions triggered by the CONV
Continuous software conversion.
PLA conversion.
Reserved.
MMR Bit Designation
ADCCP
0xFFFF0504
0x00
Read/write
DD
/2.
START
pin as a conversion input.
START
pin).
Rev. B | Page 39 of 104
ADCCN Register
Name:
Address:
Default Value:
Access:
ADCCN is an ADC negative channel selection register. This
MMR is described in Table 32.
Table 32. ADCCN MMR Bit Designation
Bit
[7:5]
[4:0]
ADCSTA Register
Name:
Address:
Default Value:
Access:
ADCSTA is an ADC status register that indicates when an ADC
conversion result is ready. The ADCSTA register contains only
one bit, ADCReady (Bit 0), representing the status of the ADC.
This bit is set at the end of an ADC conversion, generating an
ADC interrupt. It is cleared automatically by reading the
ADCDAT MMR. When the ADC is performing a conversion,
the status of the ADC can be read externally via the ADC
pin. This pin is high during a conversion. When the conversion
is finished, ADC
Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
Others
BUSY
Description
Reserved.
Negative channel selection bits.
ADC0.
ADC1.
ADC2.
ADC3.
ADC4.
ADC5.
ADC6.
ADC7.
ADC8.
ADC9.
ADC10.
ADC11.
DAC0/ADC12.
DAC1/ADC13.
DAC2/ADC14.
DAC3/ADC15.
Reserved.
AGND.
Reserved.
Reserved.
Reserved.
goes back low. This information is available
ADCCN
0xFFFF0508
0x01
Read/write
ADCSTA
0xFFFF050C
0x00
Read only
ADuC7124/ADuC7126
BUSY