ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 90

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

ADuC7121
TIMER2—WAKE-UP TIMER
Timer2 is a 32-bit wake-up timer, count down or count up, with
a programmable prescaler. The prescaler is clocked directly from
one of four clock sources, namely, the core clock (default selection),
the internal 32.768 kHz oscillator, the external 32.768 kHz
watch crystal, or the PLL undivided clock. The selected clock
source can be scaled by a factor of 1, 16, 256, or 32,768. The
wake-up timer continues to run when the core clock is disabled.
This gives a minimum resolution of 22 ns when the core is
operating at 41.78 MHz and with a prescaler of 1. Capture of
the current timer value is enabled if the Timer2 interrupt is
enabled via IRQEN[4].
The counter can be formatted as a plain 32-bit value or as
Hours:Minutes:Seconds:Hundreths.
Timer2 reloads the value from T2LD either when Timer2 over-
flows or immediately when T2CLRI is written. The Timer2
interface consists of four MMRs, as shown in Table 126.
Table 126. Timer2 Interface Registers
Register
T2LD
T2VAL
T2CLRI
T2CON
Timer2 Load Registers
T2LD is a 32-bit register, which holds the 32 bit value that is
loaded into the counter.
Name:
Address:
Default value:
Access:
Timer2 Clear Register
This 8-bit write-only MMR is written (with any value) by the
user code to refresh (reload) Timer2.
Name:
Address:
Default value:
Access:
Description
32-bit register. Holds 32-bit unsigned integers.
32-bit register. Holds 32-bit unsigned integers.
This register is read only.
8-bit register. Writing any value to this register clears
the Timer2 interrupt.
Configuration MMR.
T2LD
0xFFFF0340
0x00000000
Read and write
T2CLRI
0xFFFF034C
0x00
Write only
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Timer2 Value Register
T2VAL is a 32-bit register that holds the current value of Timer2.
Name:
Address:
Default value:
Access:
Timer2 Control Register
This 32-bit MMR configures the mode of operation for Timer2.
Name:
Address:
Default value:
Access:
Table 127. T2CON MMR Bit Designations
Bit
31:11
10:9
8
7
6
5:4
3:0
Value
00
01
10
11
00
01
10
11
0000
0100
1000
1111
T2VAL
0xFFFF0344
0x00000000
Read only
T2CON
0xFFFF0348
0x00000000
Read and write
Description
Reserved.
Clock source select.
Internal 32.768 kHz oscillator (default).
Core clock.
External 32.768kHz watch crystal.
UCLK.
Count up.
Set by the user for Timer2 to count up.
Cleared by the user for Timer2 to count down
(default).
Timer2 enable bit.
Set by the user to enable Timer2.
Cleared by the user to disable Timer2 (default).
Timer2 mode.
Set by the user to operate in periodic mode.
Cleared by the user to operate in free-running
mode (default).
Format.
Binary (default).
Reserved.
Hr:Min:Sec:Hundredths: 23 hours to 0 hour.
Hr:Min:Sec:Hundredths: 255 hours to 0 hour.
Prescaler.
Source clock divide-by-1 (default).
Source clock divide-by-16.
Source clock divide-by-256. (Use this setting in
conjunction with Timer2 Format 1,0 and
Format 1,1.)
Source clock divide-by-32,768.