ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 46

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

ADuC7121
Table 56. IDAC0PULLDOWN MMR Bit Designations
Bit
7:6
5
4
3:0
Table 57. IDAC Data Registers (Default Value = 0x00000000,
Read and Write Access)
Name
IDAC0DAT
IDAC1DAT
IDAC2DAT
IDAC3DAT
IDAC4DAT
Table 58. IDACxDAT MMR Bit Designations
Bit
31:28
27:16
15:0
Table 59. IDAC Bandwidth Registers (Default Value = 0x00,
Read and Write Access)
Name
IDAC0BW
IDAC1BW
IDAC2BW
IDAC3BW
IDAC4BW
Value
0
0
Name
Reserved
Data
Reserved
Name
Reserved
Pulldown
PLA_PD_EN
PLA Source
Value
000
Address (Hex)
0xFFFF0704
0xFFFF0710
0xFFFF071C
0xFFFF0728
0xFFFF0734
Description
These bits are set to 0 by the user.
IDAC0 pull-down.
Set to 1 by the user to pull down
the IDAC0 pin as well as power
down the IDAC0.
Set to 0 by the user to disable the
pull-down.
PLA output trigger enable.
Set to 1 by the user to enable the
PLA output to trigger the IDAC0
pull-down.
Set to 0 by the user to disable this
feature.
PLA output source for PLA output
trigger enable.
Can select the output of any
element, 0 to 15, by programming
these bits with the corresponding
binary value.
Description
These bits are reserved.
Data from IDACx.
These bits are reserved.
Address
0xFFFF0708
0xFFFF0714
0xFFFF0720
0xFFFF072C
0xFFFF0738
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Table 60. IDACxBW MMR Bit Designations
Bit
7:4
3:0
Table 61. IDAC Status Register (Default Value = 0x00, Read
and Write Access)
Name
IDACSTA
Table 62. IDACSTA MMR Bit Designations
Bit
7:2
1
0
OSCILLATOR AND PLL—POWER CONTROL
The ADuC7121 integrates a 32.768 kHz oscillator, a clock divider,
and a PLL. The PLL locks onto a multiple (1275) of the internal
oscillator to provide a stable 41.78 MHz clock for the system.
The core can operate at this frequency, or at binary submultiples
of it, to allow for power saving. The default core clock is the PLL
clock divided by 8 (CD = 3) or 5.2 MHz. The core clock frequency
can be output on the XCLK pin as described in Figure 32. Note
that when the XCLK pin is used to output the core clock, the
output signal is not buffered and is not suitable for use as a
clock source to an external device without an external buffer.
A power-down mode is available on the ADuC7121.
Name
Reserved
BW
Value
0
0
Name
Reserved
TSHUT
EXTRESLOW
Value
000
001
010
011
100
101
110
Others
Address (Hex)
0xFFFF0740
Description
The user sets these bits to 0.
Bandwidth control bits. Defines the
3 dB bandwidth of the RC low-pass
filter, assuming a 0.01 μF capacitor
on the C
IDACx.
100 kHz.
28.7 kHz.
15 kHz.
7.8 kHz.
4 kHz.
2.2 kHz.
1.2 kHz.
Not defined.
External resistor short bit.
Description
These bits are set to 0 by the user.
Thermal shutdown error status bit.
Set to 1 by the core indicating a
thermal shutdown event.
Set to 0 by the core indicating the
IDACs are within operating
temperature.
Set to 1 by the core indicating an
external resistor short.
Set to 0 by the core when
operating normally.
DAMP
_IDACx pins of the