ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 51

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

Table 69. PWMCON1 MMR Bit Designations (Address = 0xFFFF0F80, Default Value = 0x0012)
Bit
15
14
13
12
11
10
9
8:6
5
4
3
2
1
0
Name
Reserved
SYNC
PWM6INV
PWM4NV
PWM2INV
PWMTRIP
ENA
PWMCP[2:0]
POINV
HOFF
LCOMP
DIR
HMODE
PWMEN
This bit is reserved.
Enables PWM synchronization.
Set to 1 by the user to invert PWM6.
Set to 1 by the user to invert PWM4.
Set to 1 by the user to invert PWM2.
If HOFF = 0 and HMODE = 1. If HOFF = 1 and HMODE = 1, see Table 70. If not in H-Bridge mode, this bit has no effect.
PWM clock prescaler bits. Sets the UCLK divider.
Load compare registers.
Direction control.
Set to 1 by the user to enable all PWM outputs.
Description
Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low
transition on SYNC of the P0.3/MISO/PLAO[12]/SYNC pin.
Cleared by the user to ignore transitions on SYNC of the P0.3/MISO/PLAO[12]/SYNC pin.
Cleared by the user to use PWM6 in normal mode.
Cleared by the user to use PWM4 in normal mode.
Cleared by the user to use PWM2 in normal mode.
Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an
interrupt is generated.
Cleared by the user to disable the PWMTRIP interrupt.
Set to 1 by the user to enable PWM outputs.
Cleared by the user to disable PWM outputs.
000 = UCLK divide-by-2.
001 = UCLK divide-by-4.
010 = UCLK divide-by-8.
011 = UCLK divide-by-16.
100 = UCLK divide-by-32.
101 = UCLK divide-by-64.
110 = UCLK divide-by-128.
111 = UCLK divide-by-256.
Set to 1 by the user to invert all PWM outputs.
Cleared by the user to use PWM outputs as normal.
High-side off.
Set to 1 by the user to force PWM1 and PWM3 outputs high. This also forces PWM2 and PWM4 low.
Cleared by the user to use the PWM outputs as normal.
Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of the
PWM timer from 0x00 to 0x01.
Cleared by the user to use the values previously stored in the internal compare registers.
Set to 1 by the user to enable PWM1 and PWM2 as the output signals while PWM3 and PWM4 are held low.
Cleared by the user to enable PWM3 and PWM4 as the output signals while PWM1 and PWM2 are held low.
Enables H-bridge mode.
Set to 1 by the user to enable H-Bridge mode and Bits[5:2] of PWMCON1.
Cleared by the user to operate the PWMs in standard mode.
Cleared by the user to disable all PWM outputs.
Rev. 0 | Page 51 of 96
ADuC7121