ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 37

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

Table 41. FEE0PRO and FEE0HID MMR Bit Designations
Bit
31
30:0
Command Sequence for Executing a Mass Erase
FEE0DAT = 0x3CFF;
FEE0ADR = 0xFFC3;
FEE0MOD = FEE0MOD|0x8;
FEE0CON = 0x06;
FEE1DAT Register
FEE1DAT is a 16-bit data register.
Name:
Address:
Default value:
Access:
FEE1ADR Register
FEE1ADR is a 16-bit address register.
Name:
Address:
Default value:
Access:
FEE1SGN Register
FEE1SGN is a 24-bit code signature.
Name:
Address:
Default value:
Access:
FEE1PRO Register
FEE1PRO provides protection following subsequent reset MMR.
It requires a software key (see Table 42).
Name:
Address:
Default value:
Access:
Description
Read protection.
Cleared by the user to protect Block 0.
Set by the user to allow reading Block 0.
Write protection for Page 123 to Page 120, for Page 119
to Page 116, and for Page 0 to Page 3.
Cleared by the user to protect the pages in writing.
Set by the user to allow writing the pages.
FEE1DAT
0xFFFF0E8C
0xXXXX
Read and write
FEE1ADR
0xFFFF0E90
0x0000
Read and write
FEE1SGN
0xFFFF0E98
0xFFFFFF
Read only
FEE1PRO
0xFFFF0E9C
0x00000000
Read and write
//Mass erase command
//Erase key enable
Rev. 0 | Page 37 of 96
FEE1HID Register
FEE1HID provides immediate protection MMR. It does not
require any software keys (see Table 42).
Name:
Address:
Default value:
Access:
Table 42. FEE1PRO and FEE1HID MMR Bit Designations
Bit
31
30
29:0
FEE0STA Register
Name:
Address:
Default value:
Access:
FEE1STA Register
Name:
Address:
Default value:
Access:
Table 43. FEExSTA MMR Bit Designations
Bit
15:6
5
4
3
2
Description
Read protection.
Write protection for Page 127 to Page 120.
Cleared by the user to protect Block 1.
Set by the user to allow reading Block 1.
Cleared by the user to protect the pages in writing.
Set by the user to allow writing the pages.
Write protection for Page 119 to Page 116 and for Page 0
to Page 3.
Cleared by the user to protect the pages in writing.
Set by the user to allow writing the pages.
Description
Reserved.
Reserved.
Reserved.
Flash/EE interrupt status bit.
Set automatically when an interrupt occurs, that is,
when a command is complete and the Flash/EE
interrupt enable bit in the FEExMOD register is set.
Cleared when reading FEExSTA register.
Flash/EE controller busy.
Set automatically when the controller is busy.
Cleared automatically when the controller is not busy.
FEEHID
0xFFFF0EA0
0xFFFFFFFF
Read and write
FEE0STA
0xFFFF0E00
0x0000
Read and write
FEE1STA
0xFFFF0E80
0x0000
Read and write
ADuC7121