ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 50

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

ADuC7121
DIGITAL PERIPHERALS
PWM GENERAL OVERVIEW
The ADuC7121 integrates a 6-channel PWM interface. The PWM
outputs can be configured to drive an H-bridge or can be used as
standard PWM outputs. On power-up, the PWM outputs default
to H-bridge mode. This ensures that the motor is turned off by
default. In standard PWM mode, the outputs are arranged as three
pairs of PWM pins. Users have control over the period of each
pair of outputs and over the duty cycle of each individual output.
In all modes, the PWMxCOMx MMRs control the point at
which the PWM outputs change state. An example of the first pair
of PWM outputs (PWM1 and PWM2) is shown in Figure 33.
Table 68. PWM MMRs
Name
PWMCON1
PWM1COM1
PWM1COM2
PWM1COM3
PWM1LEN
PWM2COM1
PWM2COM2
PWM2COM3
PWM2LEN
PWM3COM1
PWM3COM2
PWM3COM3
PWM3LEN
PWMCON2
PWMICLR
HIGH SIDE
LOW SIDE
(PWM1)
(PWM2)
PWM1COM3
PWM1COM2
PWM1COM1
PWM1LEN
Figure 33. PWM Timing
Function
PWM control
Compare Register 1 for PWM Output 1 and PWM Output 2
Compare Register 2 for PWM Output 1 and PWM Output 2
Compare Register 3 for PWM Output 1 and PWM Output 2
Frequency control for PWM Output 1 and PWM Output 2
Compare Register 1 for PWM Output 3 and PWM Output 4
Compare Register 2 for PWM Output 3 and PWM Output 4
Compare Register 3 for PWM Output 3 and PWM Output 4
Frequency control for PWM Output 3 and PWM Output 4
Compare Register 1 for PWM Output 5 and PWM Output 6
Compare Register 2 for PWM Output 5 and PWM Output 6
Compare Register 3 for PWM Output 5 and PWM Output 6
Frequency control for PWM Output 5 and PWM Output 6
PWM convert start control
PWM interrupt clear
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The PWM clock is selectable via PWMCON1 with one of the
following values: UCLK divide-by-2, 4, 8, 16, 32, 64, 128, or
256. The length of a PWM period is defined by PWMxLEN.
The PWM waveforms are set by the count value of the 16-bit
timer and the compare registers contents as shown with the
PWM1 and PWM2 waveforms above.
The low-side waveform, PWM2, goes high when the timer
count reaches PWM1LEN, and it goes low when the timer
count reaches the value held in PWM1COM3 or when the
high-side waveform PWM1 goes low.
The high-side waveform, PWM1, goes high when the timer
count reaches the value held in PWM1COM1, and it goes low
when the timer count reaches the value held in PWM1COM2.