ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 35

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

NONVOLATILE FLASH/EE MEMORY
FLASH/EE MEMORY OVERVIEW
The ADuC7121 incorporates Flash/EE memory technology on
chip to provide the user with nonvolatile, in circuit reprogram-
mable memory space.
Similar to EEPROM, flash memory can be programmed in system
at a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often
(and more correctly) referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes no volatility, in circuit program-
mability, high density, and low cost. Incorporated in the
ADuC7121, Flash/EE memory technology allows the user
to update program code space in circuit, without the need
to replace one time programmable (OTP) devices at remote
operating nodes.
FLASH/EE MEMORY
The ADuC7121 contains two 64 kB arrays of Flash/EE memory.
In the first block, the lower 62 kB is available to the user and the
upper 2 kB of this Flash/EE memory array program contain
permanently embedded firmware, allowing in circuit serial down-
load. The 2 kB of embedded firmware also contain a power-on
configuration routine that downloads factory calibrated coefficients
to the various calibrated peripherals (band gap references and
so forth). This 2 kB embedded firmware is hidden from user code.
It is not possible for the user to read, write, or erase this page.
In the second block, all 64 kB of Flash/EE memory are available
to the user.
The 126 kB of Flash/EE memory can be programmed in circuit
using the serial download mode or the JTAG mode.
Flash/EE Memory Reliability
The Flash/EE memory arrays on the ADuC7121 are fully
qualified for two key Flash/EE memory characteristics:
Flash/EE memory cycling endurance and Flash/EE memory
data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as follows:
1.
2.
3.
4.
In reliability qualification, every half word (16-bit wide) location
of the three pages (top, middle, and bottom) in the Flash/EE
memory is cycled 10,000 times from 0x0000 to 0xFFFF.
As indicated in the Specifications section, the Flash/EE memory
endurance qualification is carried out in accordance with
JEDEC Retention Lifetime Specification A117 over the
Initial page erase sequence
Read/verify sequence a single Flash/EE
Byte program sequence memory
Second read/verify sequence endurance cycle
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industrial temperature range of –10° to +95°C. The results allow
the specification of a minimum endurance figure over a supply
temperature of 10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts are
qualified in accordance with the formal JEDEC Retention
Lifetime Specification A117 at a specific junction temperature
(T
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. Note, too, that retention
lifetime, based on activation energy of 0.6 eV, derates with
T
Serial Downloading (In-Circuit Programming)
The ADuC7121 facilitates code download via the I
port. The ADuC7121 enters serial download mode after a reset
or power cycle if the BM function of the P3.7/ BM /PLAO[11]
pin is pulled low through an external 1 kΩ resistor. This is
combined with the state of Address 0x00014 in the flash. If this
address is 0xFFFFFFFF and BM is pulled low, the part enters
download mode; if this address contains any other value, user
code is executed. When in serial download mode, the user can
download code to the full 126 kB of Flash/EE memory while the
device is in circuit in its target application hardware. A PC serial
download executable and hardware dongle are provided as part of
the development system for serial downloads via the I
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug.
FLASH/EE MEMORY SECURITY
The 126 kB of Flash/EE memory available to the user can be
read and write protected. Bit 31 of the FEE0PRO/FEE0HID MMR
protects the 126 kB from being read through JTAG and also in
I
2
J
C programming mode. The other 31 bits of this register protect
, as shown in Figure 25.
J
= 85°C). As part of this qualification procedure, the
600
450
300
150
0
30
Figure 25. Flash/EE Memory Data Retention
40
JUNCTION TEMPERATURE (°C)
55
70
85
100
125
ADuC7121
135
2
2
C serial
C port.
150