ADUC7019 Analog Devices, ADUC7019 Datasheet - Page 8

• Manufacturer Part Number: ADUC7019
• Manufacturer: Analog Devices

Specifications of ADUC7019

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 14
• Adc # Channels: 5

ADuC7019/20/21/22/24/25/26/27/28/29
Parameter
MCU CLOCK RATE
START-UP TIME
PROGRAMMABLE LOGIC ARRAY (PLA)
POWER REQUIREMENTS
ESD TESTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
All ADC channel specifications are guaranteed during normal MicroConverter core operation.
Apply to all ADC input channels.
Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
Not production tested but supported by design and/or characterization data on production release.
Measured using the factory-set default values in ADCOF and ADCGN with an external
system components; the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
The input signal can be centered on any dc common-mode voltage (V
DAC linearity is calculated using a reduced code range of 100 to 3995.
DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V V
Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
3.6 V supply, and sleep mode with 3.6 V supply.
Retention lifetime equivalent at junction temperature (T
Test carried out with a maximum of eight I/Os set to a low output level.
See the POWCON register.
Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
IOV
On the ADuC7019/20/21/22, this current must be added to the AV
From 32 kHz Internal Oscillator
From 32 kHz External Crystal
At Power-On
From Pause/Nap Mode
From Sleep Mode
From Stop Mode
Pin Propagation Delay
Element Propagation Delay
Power Supply Voltage Range
Analog Power Supply Currents
Digital Power Supply Current
Additional Power Supply Currents
Using an External Clock
HBM Passed Up To
FCIDM Passed Up To
DD
AV
DACV
IOV
IOV
IOV
ADC
DAC
AV
power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
DD
DD
DD
DD
DD
to AGND and IOV
Current
DD
Current in Normal Mode
Current in Pause Mode
Current in Sleep Mode
Current
15
13, 14
DD
to IOGND
Min
0.05
0.05
2.7
J
) = 85°C as per JEDEC Standard 22m, Method A117. Retention lifetime derates with junction temperature.
Typ
326
41.78
130
24
3.06
1.58
1.7
12
2.5
200
400
3
7
11
40
25
250
600
2
0.7
700
DD
current.
CM
) as long as this value is within the ADC voltage input range specified.
Rev. D | Page 8 of 96
Max
44
41.78
3.6
25
10
15
45
30
400
1000
4
0.5
REF
AD845
.
op amp as an input buffer stage as shown in Figure 49. Based on external ADC
Unit
kHz
MHz
MHz
ms
ns
μs
ms
ms
ns
ns
μA
μA
μA
mA
mA
mA
mA
μA
mA
mA
μA
MHz
V
μA
kV
kV
Core clock = 41.78 MHz
Test Conditions/Comments
CD
CD
T
T
CD
CD
From input pin to output pin
ADC in idle mode; all parts except ADuC7019
ADC in idle mode; ADuC7019 only
Code executing from Flash/EE
CD
CD
CD
CD
T
T
@ 1 MSPS
@ 62.5 kSPS
per DAC
2.5 V reference, T
A
A
A
A
= 85°C
= 125°C
= 85°C
= 125°C
12
12
12
12
12
12
12
12
= 0
= 0
= 7
= 7
= 3
= 0 (41.78 MHz clock)
= 0 (41.78 MHz clock)
= 7
A
= 25°C