LFEC3E-3FN256C LATTICE SEMICONDUCTOR, LFEC3E-3FN256C Datasheet - Page 162

• Manufacturer Part Number: LFEC3E-3FN256C
• Description: FPGA LatticeEC Family 3100 Cells 340MHz 130nm (CMOS) Technology 1.2V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFEC3E-3FN256C

• Package: 256FBGA
• Family Name: LatticeEC
• Device Logic Units: 3100
• Maximum Internal Frequency: 340 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 160
• Ram Bits: 56320
• In System Programmability: Yes

Lattice Semiconductor
December 2004
April 2005
May 2005
Date
Version
01.4
01.5
01.6
Ordering Information
Ordering Information
Pinout Information
Pinout Information
Pinout Information
DC & Switching
DC & Switching
Characteristics
Characteristics
Supplemental
Architecture
Architecture
Architecture
Introduction
Information
Section
Updated Hot Socketing Recommended Power Up Sequence section.
Added LFEC1, LFEC3, LFECP/EC10, LFECP/EC15 to Pin Information
Added LFEC1, LFEC3, LFECP/EC10, LFECP/EC15 to Power Supply
and NC Connections
Added LFEC1 and LFEC3 100 TQFP Pinout
Added LFEC1 and LFEC3 144 TQFP Pinout
Added LFEC1, LFEC3 and LFECP/EC10 208 PQFP Pinout
Added LFEC3, LFECP/EC10 and LFECP/EC15 256 fpBGA Pinout
Added LFECP/EC10 and LFECP/EC15 484 fpBGA Pinout
Added Lead-Free Package Designators
Added Lead-Free Ordering Part Numbers
Updated list of technical notes.
EBR memory support section has been updated with clarification.
Updated sysIO buffer pair section.
Hot Socketing Specification has been updated.
DC Electrical Characteristics table (I
Supply Current (Standby) table has been updated.
Initialization Supply Current table has been updated.
External Switching Characteristics section has been updated.
Removed t
t
sysCONFIG Port Timing Specifications (t
been updated.
Added LFECP/EC33 Pinout Information
Pin Information Summary table has been updated.
Power Supply and NC Connection table has been updated.
484-fpBGA logic connection has been updated (Ball # J6, J17, P6 and
P17 for ECP/EC33 are now called VCCPLL).
672-fpBGA logic connection has been updated (Ball # K19, L8, U19, U8
for ECP/EC33 are now called VCCPLL).
ECP/EC33 EBR SRAM Bits and Blocks have been updated to 498K
and 54 respectively.
Table 2-10 has been updated (ECP/EC33 EBR SRAM Bits and Blocks
have been updated to 498K and 54 respectively.)
Recommended Power Up Sequence section has been removed.
Supply Current (Standby) table has been updated.
Initialization Supply Current table has been updated.
Vos test condition has been updated to (VOP+VOM)/2.
Register-to-Register performance table has been updated (rev. G 0.27).
External switching characteristics have been updated (rev. G 0.27).
Internal timing parameters have been updated (rev. G 0.27).
Timing adders have been updated (rev. G 0.27).
sysCONFIG port timing specifications have been updated.
Pin Information Summary table has been updated.
Power Supply and NC Connection table has been updated.
OPN list has been updated.
RST
specifications have been updated.
7-2
RSTW
spec. from PLL Parameter table.
LatticeECP/EC Family Data Sheet
Change Summary
IL
, I
IH
BSCL,
) has been updated.
t
IODISS,
Revision History
t
PRGMRJ
) have