LFXP20C-5FN256C LATTICE SEMICONDUCTOR, LFXP20C-5FN256C Datasheet - Page 62

• Manufacturer Part Number: LFXP20C-5FN256C
• Description: FPGA LatticeXP Family 20000 Cells 400MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFXP20C-5FN256C

• Package: 256FBGA
• Family Name: LatticeXP
• Device Logic Units: 20000
• Maximum Internal Frequency: 400 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 188
• Ram Bits: 405504
• Re-programmability Support: Yes

Lattice Semiconductor
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
Notes:
1. “n” is a row/column PIC number.
2. The DDR interface is designed for memories that support one DQS strobe per eight bits of data. In some packages, all the potential DDR
3. The definition of the PIC numbering is provided in the Signal Names column of the Signal Descriptions table in this data sheet.
data (DQ) pins may not be available.
with DQS Strobe
PICs Associated
PIO within PIC
A
B
A
B
A
B
A
B
A
B
A
B
A
B
4-3
Complement
Complement
Complement
Complement
Complement
Complement
Complement
Polarity
True
True
True
True
True
True
True
LatticeXP Family Data Sheet
Pinout Information
and Data (DQ) Pins
DDR Strobe (DQS)
[Edge]DQSn
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ