EVAL-CN0160-EB1Z Analog Devices Inc, EVAL-CN0160-EB1Z Datasheet - Page 3

• Manufacturer Part Number: EVAL-CN0160-EB1Z
• Description: BOARD, EVAL, FOR CN0160
• Manufacturer: Analog Devices Inc
• Type: USB Peripheral Isolatorr
• Series: -r

Specifications of EVAL-CN0160-EB1Z

• Kit Contents: Board
• Mcu Supported Families: CN0160
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: CN0160
• Design Resources: USB Peripheral Isolator Circuit (CN0160)
• Main Purpose: Interface, Isolator USB Peripheral
• Embedded: No
• Utilized Ic / Part: ADuM4160, ADP3338
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Circuit Note
Power can be provided as 5 V through the VBUSx pins, and the
3.3 V signaling voltage is created by an internal 3.3 V regulator
at the VDDx pin. Alternatively, the 3.3 V power can also be
provided to VBUSx and VDDx, and the part uses the external
supply directly, disabling the internal regulator.
This option was provided to allow the
from a 5 V USB cable or from an available 5 V or 3.3 V rail
supplied by a peripheral. In the circuit shown, it was connected
to accept 5 V from each side, and the internal regulators are
active.
The ADuM4160 has an option to delay application of the
upstream pull-up under control of the peripheral. This
function is controlled by the PIN input. In this application,
the PIN input is jumpered high so that the upstream pull-up
is applied as soon as peripheral power is applied. In other
applications, it can be connected to a GPIO pin of a controller, a
fixed delay circuit can be applied, or it can be connected as
shown in this circuit. It is the designer’s choice how to use this
functionality.
Protection devices are included in this circuit. These were
chosen from manufacturers that have a wide variety of
components available, and the particular components were
chosen to allow them to be replaced by 0 Ω shorts, thereby
removing them from the circuit. The choice of protection
should be reviewed by the designer and can range from
no external protection to a full complement of transient
suppressors and filter elements. The circuit elements
included in this circuit show a typical high protection
configuration.
When the circuit is functioning, packets are detected and data is
shuttled from one side of the isolation barrier to the other. Data
shown in Figure 2 and Figure 3 demonstrates a typical full
speed transaction both as time domain data and as an eye
diagram. Features to note in the real-time data are the passive
idle state at the start of the packet, which transitions to a driven
J, and then the end of the packet at the end of the transaction
showing as a single-ended zero state followed by idle J. It is the
automatic flow of control and the handling of these special logic
states that make the ADuM4160 unique in the marketplace.
The data shown in Figure 2 and Figure 3below are generated as
part of the USB-IF qualification process. Figure 2 shows a test
data packet from the ADuM4160 upstream port to the host.
Portions to note are the leading idle state where the passive
resistor network holds an idle J state. The center portion of the
packet is a mix of J and K states. The right side of the packet is
an EOP (end of packet) marker, which is a single-ended 0
followed by a driven J, which transitions to an idle J.
ADuM4160
to run either
Rev. A | Page 3 of 5
The following are applicable test references:
•
•
•
Figure 3 is a full speed eye diagram showing that the
ADuM4160 provides an adequate open eye, staying well out of
the keep out region. Similar data is also taken for low speed
evaluation.
Upstream full speed signal quality test reference—USB 2.0
Specification, Section 7.1.11., Section 7.1.2.1.
Upstream full speed rise time test reference—USB 2.0
Specification, Section 7.1.11., Section 7.1.2.2.
Upstream full speed fall time test reference—USB 2.0
Specification, Section 7.1.11., Section 7.1.2.2.
Figure 3. Full Speed Eye Diagram Showing Exclusion Zone
Figure 2. Full Speed Test Packet Traffic Driven By
the Upstream ADuM4160 Port
CN-0160