DP83932CVF20 National Semiconductor, DP83932CVF20 Datasheet - Page 33

• Manufacturer Part Number: DP83932CVF20
• Manufacturer: National Semiconductor

Specifications of DP83932CVF20

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

4 0 SONIC Registers
4 3 4 Transmit Control Register
(RA
This register is used to program the SONIC’s transmit actions and provide status information after a packet has been transmit-
ted (Figure 4-7) At the beginning of transmission bits 15 14 13 and 12 from the TXpkt config field are loaded into the TCR to
configure the various transmit modes (see Section 3 5 1 1) When the transmission ends bits 10 – 0 indicate status information
and are set to a ‘‘1’’ when the corresponding condition is true These bits along with the number of collisions information are
written into the TXpkt status field at the end of transmission (see Section 3 5 1 2) Bits 9 and 5 are cleared after the TXpkt status
field has been written Bits 10 7 6 and 1 are cleared at the commencement of the next transmission while bit 8 is set at this
time
A hardware reset sets bits 8 and 0 to a ‘‘1’’ and bit 1 to a 0 This register is unaffected by a software reset
Bit
15
14
13
12
11
10
k
r
e
PINT POWC CRCI EXDIS
r w
5 0
15
read only r w
l
PINT PROGRAMMABLE INTERRUPT
This bit allows transmit interrupts to be generated under software control The SONIC will issue an interrupt (PINT in
the Interrupt Status Register) immediately after reading a TDA and detecting that PINT is set in the TXpkt config
field
Note In order for PINT to operate properly it must be set and reset in the TXpkt config field by alternating TDAs This is necessary because after
PINT has been issued in the ISR PINT in the Transmit Control Register must be cleared before it is set again in order to have the interrupt issued for
another packet The only effective way to do this is to set PINT to a 1 no more often than every other packet
POWC PROGRAM ‘‘OUT OF WINDOW COLLISION’’ TIMER
This bit programs when the out of window collision timer begins
0 timer begins after the Start of Frame Delimiter (SFD)
1 timer begins after the first bit of preamble
CRCI CRC INHIBIT
0 transmit packet with 4-byte FCS field
1 transmit packet without 4-byte FCS field
EXDIS DISABLE EXCESSIVE DEFERRAL TIMER
0 excessive deferral timer enabled
1 excessive deferral timer disabled
Must be 0
EXD EXCESSIVE DEFERRAL
Indicates that the SONIC has been deferring for 3 2 ms The transmission is aborted if the excessive deferral timer is
enabled (i e EXDIS is reset) This bit can only be set if the excessive deferral timer is enabled
e
r w
14
3h)
e
read write
r w
13
r w
12
PINT
POWC PROGRAMMED OUT OF WINDOW COLLISION TIMER
CRCI
EXDIS DISABLE EXCESSIVE DEFERRAL TIMER
EXD
DEF
NCRS NO CRS
CRSL
EXC
OWC
PMB
FU
BCM
PTX
Field
(Continued)
11
0
r
PROGRAMMABLE INTERRUPT
CRC INHIBIT
EXCESSIVE DEFERRAL
DEFERRED TRANSMISSION
CRS LOST
EXCESSIVE COLLISIONS
OUT OF WINDOW COLLISION
PACKET MONITORED BAD
FIFO UNDERRUN
BYTE COUNT MISMATCH
PACKET TRANSMITTED OK
FIGURE 4-7 Transmit Control Register
EXD
10
r
DEF NCRS CRSL EXC
9
r
8
r
33
Description
Meaning
7
r
6
r
OWC
5
r
4
0
r
PMB
3
r
FU
2
r
BCM
1
r
PTX
0
r