AD6649BCPZ Analog Devices Inc, AD6649BCPZ Datasheet - Page 6

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AD6649BCPZ

Manufacturer Part Number
AD6649BCPZ
Description
IC IF RCVR 14BIT 250MSPS 64LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD6649BCPZ

Leaded Process Compatible
Yes
Rohs Compliant
Yes
Resolution (bits)
14bit
Sampling Rate
250MSPS
Input Channel Type
Differential
Data Interface
Serial, SPI
Supply Voltage Range - Analog
1.7V To 1.9V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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AD6649
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input,
DCS enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
SYNC INPUT
LOGIC INPUT (CSB)
LOGIC INPUT (SCLK)
LOGIC INPUT/OUTPUT (SDIO)
LOGIC INPUTS (OEB, PDWN)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
Input Capacitance
Input Resistance
High Level Input Current
Low Level Input Current
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
2
3
3
2
Rev. 0 | Page 6 of 40
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1
1.0 V internal reference,
Min
0.3
AGND
0.9
+10
−22
8
AGND
1.2
AGND
−5
−5
12
1.22
0
−5
−80
1.22
0
45
−5
1.22
0
45
−5
1.22
0
45
−5
CMOS/LVDS/LVPECL
CMOS/LVDS
Typ
4
10
1
16
26
2
26
2
26
5
0.9
0.9
Max
3.6
AVDD
1.4
+22
−10
12
AVDD
AVDD
0.6
+5
+5
20
2.1
0.6
+5
−45
2.1
0.6
70
+5
2.1
0.6
70
+5
2.1
0.6
70
+5
Unit
V
V p-p
V
V
μA
μA
pF
V
V
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA

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