LCMXO2-1200HC-4TG100CR1 Lattice, LCMXO2-1200HC-4TG100CR1 Datasheet - Page 14

• Manufacturer Part Number: LCMXO2-1200HC-4TG100CR1
• Description: IC PLD 1280LUTS 80I/O 100TQFP
• Manufacturer: Lattice

Specifications of LCMXO2-1200HC-4TG100CR1

• Programmable Type: *
• Number Of Macrocells: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1135

Lattice Semiconductor
Table 2-5. sysMEM Block Configurations
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. EBR initialization data can be
loaded from the UFM. To maximize the number of UFM bits, initialize the EBRs used in your design to an all-zero
pattern. Initializing to an all-zero pattern does not use up UFM bits. MachXO2 devices have been designed such
that multiple EBRs share the same initialization memory space if they are initialized to the same pattern.
By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block
can also be utilized as a ROM.
Memory Cascading
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual, Pseudo-Dual Port and FIFO Modes
Figure 2-8 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM
modes, the input data and addresses for the ports are registered at the input of the memory array. The output data
of the memory is optionally registered at the memory array output.
Single Port
True Dual Port
Pseudo Dual Port
FIFO
Memory Mode
2-10
Configurations
4,096 x 2
2,048 x 4
1,024 x 9
4,096 x 2
2,048 x 4
1,024 x 9
4,096 x 2
2,048 x 4
1,024 x 9
4,096 x 2
2,048 x 4
1,024 x 9
8,192 x 1
8,192 x 1
8,192 x 1
512 x 18
8,192 x 1
512 x 18
MachXO2 Family Data Sheet
Architecture