LCMXO2-1200HC-4TG100CR1 Lattice, LCMXO2-1200HC-4TG100CR1 Datasheet - Page 33

• Manufacturer Part Number: LCMXO2-1200HC-4TG100CR1
• Description: IC PLD 1280LUTS 80I/O 100TQFP
• Manufacturer: Lattice

Specifications of LCMXO2-1200HC-4TG100CR1

• Programmable Type: *
• Number Of Macrocells: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1135

Lattice Semiconductor
Figure 2-21. I
Table 2-15 describes the signals interfacing with the I
Table 2-15. I
Hardened SPI IP Core
Every MachXO2 device has a hard SPI IP core that can be configured as a SPI master or slave. When the IP core
is configured as a master it will be able to control other SPI enabled chips connected to the SPI bus. When the core
is configured as the slave, the device will be able to interface to an external SPI master. The SPI IP core on
MachXO2 devices supports the following functions:
SCLI
SCLO
SCLOEN
SDAI
SDAO
SDAOEN
IRQO
• Configurable Master and Slave modes
• Full-Duplex data transfer
• Mode fault error flag with CPU interrupt capability
• Double-buffered data register
• Serial clock with programmable polarity and phase
• LSB First or MSB First Data Transfer
• Interface to custom logic through 8-bit WISHBONE interface
Signal Name
2
C Core Signal Description
2
C Core Block Diagram
I/O
O
O
O
O
O
I
I
Routing
Logic/
Core
I
I
I
I
I
I
Interrupt signal for processor. The signal will be sent to the host through SCI.
2
2
2
2
2
2
C clock line input, can be used for both Slave mode and Master mode
C clock line output, can only be used for Master mode
C clock line output enable, active low. Can only be used for Master mode
C data line input, for both slave and master modes
C data line output, for both slave and master modes
C data line output enable, active low. For both slave and master modes
EFB
WISHBONE
Interface
EFB
2
Configuration
C cores.
2-29
Registers
Logic
I
2
C
I
2
C Function
Description
Control
Control
Power
Logic
MachXO2 Family Data Sheet
SDA
SCL
Architecture