LCMXO2-1200HC-4MG132CR1 Lattice, LCMXO2-1200HC-4MG132CR1 Datasheet - Page 11

• Manufacturer Part Number: LCMXO2-1200HC-4MG132CR1
• Description: IC PLD 1280LUTS 105I/O 132CSBGA
• Manufacturer: Lattice

Specifications of LCMXO2-1200HC-4MG132CR1

• Programmable Type: *
• Number Of Macrocells: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1134

Lattice Semiconductor
Eight secondary high fanout nets are generated from eight 8:1 muxes as shown in Figure 2-6. One of the eight
inputs to the secondary high fanout net input mux comes from dual function clock pins and the remaining seven
come from internal routing.
Figure 2-6. Secondary High Fanout Nets for MachXO2 Devices
sysCLOCK Phase Locked Loops (PLLs)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The MachXO2-640U, MachXO2-1200/U
and larger devices have one or more sysCLOCK PLL. CLKI is the reference frequency input to the PLL and its
source can come from an external I/O pin or from internal routing. CLKFB is the feedback signal to the PLL which
can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference fre-
quency and thus synthesize a higher frequency clock output.
The MachXO2 sysCLOCK PLLs support high resolution (16-bit) fractional-N synthesis. Fractional-N frequency syn-
thesis allows the user to generate an output clock which is a non-integer multiple of the input frequency. For more
information about using the PLL with Fractional-N synthesis, please see TN1199,
Design and Usage
Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The
output dividers can have a value from 1 to 128. The CLKOS2 and CLKOS3 dividers may also be cascaded together
to generate low frequency clocks. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the
MachXO2 clock distribution network directly or general purpose routing resources can be used.
Guide.
Clock Pads
1
Routing
7
2-7
8:1
8:1
8:1
8:1
8:1
8:1
8:1
8:1
Secondary High
Secondary High
Secondary High
Secondary High
Secondary High
Secondary High
Secondary High
Secondary High
Fanout Net 0
Fanout Net 1
Fanout Net 2
Fanout Net 3
Fanout Net 4
Fanout Net 5
Fanout Net 6
Fanout Net 7
MachXO2 Family Data Sheet
MachXO2 sysCLOCK PLL
Architecture