LCMXO2-1200HC-4MG132CR1 Lattice, LCMXO2-1200HC-4MG132CR1 Datasheet - Page 24

• Manufacturer Part Number: LCMXO2-1200HC-4MG132CR1
• Description: IC PLD 1280LUTS 105I/O 132CSBGA
• Manufacturer: Lattice

Specifications of LCMXO2-1200HC-4MG132CR1

• Programmable Type: *
• Number Of Macrocells: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1134

Lattice Semiconductor
More information on the input gearbox is available in TN1203,
Devices.
Output Gearbox
Each PIC on the top edge has a built-in 8:1 output gearbox. Each of these output gearboxes may be programmed
as a 7:1 serializer or as one ODDRX4 (8:1) gearbox or as two ODDRX2 (4:1) gearboxes. Table 2-10 shows the
gearbox signals.
Table 2-10. Output Gearbox Signal List
The gearboxes have three stage pipeline registers. The first stage registers sample the low-speed input data on the
low-speed system clock. The second stage registers transfer data from the low-speed clock registers to the high-
speed clock registers. The third stage pipeline registers controlled by high-speed edge clock shift and mux the
high-speed data out to the sysIO buffer. Figure 2-17 shows the output gearbox block diagram.
Q
D[7:0]
Video TX(7:1): D[6:0]
GDDRX4(8:1): D[7:0]
GDDRX2(4:1)(IOL-A): D[3:0]
GDDRX2(4:1)(IOL-C): D[7:4]
SCLK
ECLK [1:0]
RST
Name
I/O Type
Output
Input
Input
Input
Input
2-20
Implementing High-Speed Interfaces with MachXO2
High-speed data output
Low-speed data from device core
Slow-speed system clock
High-speed edge clock
Reset
Description
MachXO2 Family Data Sheet
Architecture