LCMXO2-1200ZE-1MG132IR1 Lattice, LCMXO2-1200ZE-1MG132IR1 Datasheet - Page 37

• Manufacturer Part Number: LCMXO2-1200ZE-1MG132IR1
• Description: IC PLD 1280LUTS 105I/O 132CSBGA
• Manufacturer: Lattice

Specifications of LCMXO2-1200ZE-1MG132IR1

• Programmable Type: *
• Number Of Macrocells: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1143

Architecture
Lattice Semiconductor
MachXO2 Family Data Sheet
then triggers download from the on-chip configuration Flash memory after reaching the V
level specified in
PORUP
the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. For devices
without voltage regulators (ZE and HE devices), V
is the same as the V
supply voltage. For devices with
CCINT
CC
voltage regulators (HC devices), V
is regulated from the V
supply voltage. From this voltage reference, the
CCINT
CC
time taken for configuration and entry into user mode is specified as Flash Download Time (t
) in the DC
REFRESH
and Switching Characteristics section of this data sheet. Before and during configuration, the I/Os are held in tri-
state. I/Os are released to user functionality once the device has finished configuration. Note that for HC devices, a
separate POR circuit monitors external V
voltage in addition to the POR circuit that monitors the internal post-
CC
regulated power supply voltage level.
Once the device enters into user mode, the POR circuitry can optionally continue to monitor V
levels. If
CCINT
V
drops below V
level (with the bandgap circuitry switched on) or below V
level (with the
CCINT
PORDNBG
PORDNSRAM
bandgap circuitry switched off to conserve power) device functionality cannot be guaranteed. In such a situation
the POR issues a reset and begins monitoring the V
and V
voltage levels. V
and V
CCINT
CCIO
PORDNBG
PORDNSRAM
are both specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data
sheet.
Note that once a ZE or HE device enters user mode, users can switch off the bandgap to conserve power. When
the bandgap circuitry is switched off, the POR circuitry also shuts down. The device is designed such that a mini-
mal, low power POR circuit is still operational (this corresponds to the V
reset point described in the
PORDNSRAM
paragraph above). However this circuit is not as accurate as the one that operates when the bandgap is switched
on. The low power POR circuit emulates an SRAM cell and is biased to trip before the vast majority of SRAM cells
flip. If users are concerned about the V
supply dropping below V
(min) they should not shut down the bandgap
CC
CC
or POR circuit.
Configuration and Testing
This section describes the configuration and testing features of the MachXO2 family.
IEEE 1149.1-Compliant Boundary Scan Testability
All MachXO2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access
port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port shares its power supply with V
CCIO
Bank 0 and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards.
For more details on boundary scan test, see AN8066,
Boundary Scan Testability with Lattice sysIO Capability
and
TN1087,
Minimizing System Interruption During Configuration Using TransFR
Technology.
Device Configuration
All MachXO2 devices contain two ports that can be used for device configuration. The Test Access Port (TAP),
2
which supports bit-wide configuration and the sysCONFIG port which supports serial configuration through I
C or
SPI/SPIm. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard
1532 In-System Configuration specification. There are various ways to configure a MachXO2 device:
1. Internal Flash Download
2. JTAG
3. Standard Serial Peripheral Interface (SPI and SPIm modes) – interface to boot PROM memory
4. System microprocessor to drive a serial slave SPI port (SSPI mode)
2
5. Standard I
C Interface to system microprocessor or to boot PROM memory
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