STM32F217ZET6 STMicroelectronics, STM32F217ZET6 Datasheet - Page 157

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STM32F217ZET6

Manufacturer Part Number
STM32F217ZET6
Description
MCU ARM 512KB FLASH 144LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F217ZET6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, LIN, MMC, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
114
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
132K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 24x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-11188

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STM32F215xx, STM32F217xx
Table 88.
22-Apr-2011
Date
Document revision history (continued)
(continued)
Revision
4
Updated t
APB1
TIMx connected to the APB2
Changed t
t
AC waveforms and measurement
Added
updated
Updated V
characteristics.
Updated
Updated R
Updated t
Updated
Modified FSMC_NOE waveform in
multiplexed SRAM/PSRAM/NOR read
FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK
period, changed t
AIV)
NWEH)
Synchronous multiplexed NOR/PSRAM read
Synchronous multiplexed PSRAM write
Synchronous non-multiplexed NOR/PSRAM read
Figure 60: Synchronous non-multiplexed PSRAM write
Changed t
t
modified t
Table
Updated R typical value in
characteristics.Updated note 2 in
Table
Modified t
waveforms for I/O space write
Modified FSMC_NCEx signal in
waveforms for read
write
memory read
common memory write
Specified Full speed (FS) mode for
peripheral-only connection in FS mode
host-only connection in FS
f(SCK)
d(CLKH-NOEH)
, t
Doc ID 17050 Rev 4
d(CLKH-NOEH)
access,
74.
70,
, and updated data latency from 1 to 0 in
domain. Modified t
to t
Table 52: USB OTG FS DC electrical characteristics
Table 53: USB OTG FS electrical
Table 61: ADC characteristics
Table 66: Embedded internal reference
Table
res(TIM)
f(SCL)
START
w(CLK)
h(NIOWR-D)
w(SCKH)
d(CLKH-NExH
DD
AIN
Figure 69: NAND controller waveforms for common
minimum value in
access, and
to t
equation. Updated
in
71,
in
minimum value in
in
d(CLKL-NOEH)
d(CLKH-NExH
Table 47: I2C characteristics
Table 64: TS
to t
to t
Table 45: Characteristics of TIMx connected to the
Table
access,
in
w(SCLH)
d(CLKL-NOEH)
) to t
Figure 66: PC Card/CompactFlash controller
access.
res(TIM)
72,
d(CLKL-NExH)
Figure 70: NAND controller waveforms for
Table 65: VBAT monitoring
mode.
Figure 68: NAND controller waveforms for
, t
Table
) to t
domain.
, t
Changes
access.
w(SCKL)
characteristics.
d(CLKH-NWEH)
Table 57: Ethernet DC electrical
and f
Figure 67: NAND controller
Table 63: DAC
Table
d(CLKL-NExH)
circuit.
Table
, and t
Figure 53: Asynchronous non-
73, and
Figure 85: USB OTG HS
EXT
to t
waveforms. Shifted end of
, t
and R
and
67,
timings,
71,
d(CLKH-AIV)
d(CLKH-NWEH)
Table 46: Characteristics of
w(SCLL)
characteristics.
Table
Table
Figure 86: USB OTG HS
Table
timings,
AIN
to t
, t
and
Figure 57:
d(CLKH-AIV)
Figure 59:
characteristics.
, t
voltage.
d(CLKL-NWEH)
equation.
68,
74.
timings, and
72,
r(SCK)
Figure 37: I2C bus
to t
Revision history
Table
Figure 58:
Table
to t
d(CLKL-AIV)
timings,
to t
d(CLKL-
to t
69,
r(SCL)
and
73, and
, and
d(CLKL-
157/158
, and
,

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