STM32F207ZGT6 STMicroelectronics, STM32F207ZGT6 Datasheet - Page 23

• Manufacturer Part Number: STM32F207ZGT6
• Description: MCU ARM 1024KB FLASH 144LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F207ZGT6

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, LIN, MMC, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 132K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 24x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Cpu Family: STM32
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 120MHz
• Total Internal Ram Size: 132KB
• # I/os (max): 114
• Number Of Timers - General Purpose: 14
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Dac: 2(2-chx12-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11177

STM32F205xx, STM32F207xx
●
Figure 6.
1. This figure is valid both whatever the internal reset mode (ON or OFF).
In this mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the
1.2 V logic which is not reset by the NRST pin, when the internal voltage regulator in
OFF.
Regulator OFF/internal reset OFF
On WLCSP66 package, this mode activated by connecting REGOFF to V
IRROFF to V
is available only on the WLCSP package. It allows to supply externally a 1.2 V voltage
source through V
The following conditions must be respected:
–
–
–
Otherwise, PA0 should be asserted low externally during POR until V
1.8 V (see
V
between power domains (see
PA0 should be kept low to cover both conditions: until V
1.08 V, and until V
NRST should be controlled by an external reset controller to keep the device
under reset when V
DD
Startup in regulator OFF: slow V
- power-down reset risen after V
should always be higher than V
DD
. IRROFF cannot be activated in conjunction with REGOFF. This mode
Figure
CAP_1
7).
DD
and V
DD
Doc ID 15818 Rev 6
reaches 1.65 V.
is below 1.65 V (see
CAP_2
Figure
pins, in addition to V
CAP_1
6).
CAP_1
DD
slope
and V
/V
Figure
CAP_2
CAP_2
7).
DD
stabilization
.
to avoid current injection
CAP_1
and V
CAP_2
SS
DD
Description
and
reaches
reach
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