ADN2819ACP-CML Analog Devices Inc, ADN2819ACP-CML Datasheet
ADN2819ACP-CML
Specifications of ADN2819ACP-CML
Related parts for ADN2819ACP-CML
ADN2819ACP-CML Summary of contents
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FEATURES Meets SONET requirements for jitter transfer/generation/tolerance Quantizer sensitivity typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range Single reference clock frequency for ...
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ADN2819 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Definition of Terms.......................................................................... 9 Maximum, Minimum, and Typical Specifications ................... 9 Input Sensitivity and Input Overdrive....................................... 9 ...
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SPECIFICATIONS Table VCC = V A MIN MAX MIN Parameter QUANTIZER—DC CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Input Common-Mode Level Differential Input Sensitivity Input Overdrive Input Offset Input rms Noise QUANTIZER—AC CHARACTERISTICS ...
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ADN2819 Parameter Hysteresis (Electrical) (continued) LOSS OF LOCK DETECTOR (LOL) Loss of Lock Response Time POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW Jitter Peaking Jitter Generation Jitter Tolerance CML OUTPUTS (CLKOUTP/N, DATAOUTP/N) Single-Ended Output Swing ...
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Parameter Setup Time Hold Time REFCLK DC INPUT CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Common-Mode Level TEST DATA DC INPUT CHARACTERISTICS Peak-to-Peak Differential Input Voltage LVTTL DC INPUT CHARACTERISTICS Input High Voltage Input Low Voltage Input Current 5 Input ...
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ADN2819 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Lead Temperature (Soldering 10 sec) Stresses above those listed under Absolute Maximum Ratings may cause ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 3. Pin Function Descriptions Pin Number Mnemonic Type 1 THRADJ AI 2, 26, 28, Pad VCC 16, 19, 22, 27, VEE P 29, 33, 34, 42, 43 VREF AO ...
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ADN2819 CLKOUTP DATAOUTP HYSTERESIS (dB) Figure 5. LOS Hysteresis OC-3, –40°C, 3 – 1 PRBS Input Pattern, R OUTP ...
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DEFINITION OF TERMS MAXIMUM, MINIMUM, AND TYPICAL SPECIFICATIONS Specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. Typical specifications are the mean of the distribution of the data for that ...
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ADN2819 LOS RESPONSE TIME The LOS response time is the delay between the removal of the input signal and indication of loss of signal (LOS) at SDOUT. The ADN2819’s response time is 300 ns typ when the inputs are dc-coupled. ...
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OC3_JIT_TOLERANCE GBE_JIT_TOLERANCE OC3_JIT_TRANSFER GBE_JIT_TRANSFER 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 –5.0 –5.5 –6.0 –6.5 –7.0 –7.5 –8.0 –8.5 –9.0 –9.5 –10.0 1k Table 4. Jitter Transfer and Tolerance: SONET Spec vs. ADN2819 Jitter Transfer ADN2819 ...
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ADN2819 THEORY OF OPERATION The ADN2819 is a delay-locked and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that ...
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The gain of the loop integrator is small for high jitter frequencies, so larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. Large phase errors at high jitter ...
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ADN2819 FUNCTIONAL DESCRIPTION MULTIRATE CLOCK AND DATA RECOVERY The ADN2819 will recover clock and data from serial bit streams at OC-3, OC-12, OC-48, and GbE data rates as well as the 15/14 FEC rates. The output of the 2.5 GHz ...
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ADN2819 VCC REFCLKP NC REFCLKN 100kΩ 100kΩ XO1 CRYSTAL 19.44MHz OSCILLATOR XO2 REFSEL Figure 19. Crystal Oscillator Configuration The ADN2819 can accept any of the following reference clock frequencies: 19.44 MHz, 38.88 MHz, and 77.76 MHz at LVTTL/ LVCMOS/LVPECL/LVDS levels, ...
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ADN2819 ADN2819 PIN NIN 50Ω VREF SQUELCH MODE When the squelch input is driven to a TTL high state, the clock and data outputs are set to the zero state to suppress down- stream processing. If desired, this pin can ...
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APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance. Power Supply Connections and Ground Planes Use of one low impedance ground plane to both analog and digital grounds is recommended. The VEE pins ...
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ADN2819 VCC 10µF VCC 0.1µF 50Ω TIA C 50Ω IN VCC µC 19.44MHz VCC VCC 100Ω 100Ω 100Ω 100Ω 0.1µ F 0.1µ F ADN2819 Figure 23. AC-Coupled Output Configuration 4 × 100Ω µC 0.1µF 1nF ...
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CHOOSING AC-COUPLING CAPACITORS The choice of ac-coupling capacitors at the input (PIN, NIN) and output (DATAOUTP, DATAOUTN) of the ADN2819 must be chosen such that the device works properly at the lower OC-3 and higher OC-48 data rates. When choosing ...
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ADN2819 DC-COUPLED APPLICATION The inputs to the ADN2819 can also be dc-coupled. This may be necessary in burst mode applications where there are long periods of CIDs and baseline wander cannot be tolerated. If the inputs to the ADN2819 are ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model ADN2819ACP-CML ADN2819ACP-CML-RL 1 ADN2819ACPZ-CML 1 ADN2819ACPZ-CML-RL EVAL-ADN2819-CML Free. 7.00 BSC SQ 0.60 MAX 36 TOP 6.75 VIEW BSC SQ 0.50 0.40 25 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.50 BSC ...
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ADN2819 NOTES Rev Page ...
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NOTES Rev Page ADN2819 ...
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ADN2819 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02999–0–5/04(B) Rev Page ...