AD800-52BRZ Analog Devices Inc, AD800-52BRZ Datasheet

AD800-52BRZ

Manufacturer Part Number

AD800-52BRZ

Description

IC CLK\DATA RECOVERY PLL 20SOIC

Manufacturer

Analog Devices Inc

Type

Clock and Data Recovery (CDR)r

Datasheet

1.AD800-52BRZRL.pdf (12 pages)

Specifications of AD800-52BRZ

Output

Differential

Frequency - Max

51.84MHz

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

20-SOIC (7.5mm Width)

Frequency-max

51.84MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Voltage - Supply

Input

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

AD800-52BRZ

Manufacturer:

ADI/亚德诺

Quantity:

20 000

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PRODUCT DESCRIPTION

The AD800 and AD802 employ a second order phase-locked

loop architecture to perform clock recovery and data retiming

on Non-Return to Zero, NRZ, data. This architecture is

capable of supporting data rates between 20 Mbps and 160

Mbps. The products described here have been defined to work

with standard telecommunications bit rates. 45 Mbps DS-3 and

52 Mbps STS-1 are supported by the AD800-45 and

AD800-52 respectively. 155 Mbps STS-3 or STM-1 are

supported by the AD802-155.

Unlike other PLL-based clock recovery circuits, these devices

do not require a preamble or an external VCXO to lock onto

input data. The circuit acquires frequency and phase lock using

two control loops. The frequency acquisition control loop

initially acquires the clock frequency of the input data. The

phase-lock loop then acquires the phase of the input data, and

ensures that the phase of the output signals track changes in the

phase of the input data. The loop damping of the circuit is

dependent on the value of a user selected capacitor; this defines

jitter peaking performance and impacts acquisition time. The

devices exhibit 0.08 dB jitter peaking, and acquire lock on

random or scrambled data within 4 10

using a damping factor of 5.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

FEATURES

Standard Products

Accepts NRZ Data, No Preamble Required

Recovered Clock and Retimed Data Outputs

Phase-Locked Loop Type Clock Recovery—No Crystal

Random Jitter: 20 Peak-to-Peak

Pattern Jitter: Virtually Eliminated

10KH ECL Compatible

Single Supply Operation: –5.2 V or +5 V

Wide Operating Temperature Range: –40 C to +85 C

44.736 Mbps—DS-3

51.84 Mbps—STS-1

155.52 Mbps—STS-3 or STM-1

Required

bit periods when

Clock Recovery and Data Retiming

During the process of acquisition the frequency detector

provides a Frequency Acquisition (FRAC) signal which

indicates that the device has not yet locked onto the input data.

This signal is a series of pulses which occur at the points of cycle

slip between the input data and the synthesized clock signal.

Once the circuit has acquired frequency lock no pulses occur at

the FRAC output.

The inclusion of a precisely trimmed VCO in the device

eliminates the need for external components for setting center

frequency, and the need for trimming of those components. The

VCO provides a clock output within 20% of the device center

frequency in the absence of input data.

The AD800 and AD802 exhibit virtually no pattern jitter, due

to the performance of the patented phase detector. Total loop

jitter is 20 peak-to-peak. Jitter bandwidth is dictated by mask

programmable fractional loop bandwidth. The AD800, used for

data rates < 90 Mbps, has been designed with a nominal loop

bandwidth of 0.1% of the center frequency. The AD802, used

for data rates in excess of 90 Mbps, has a loop bandwidth of

0.08% of center frequency.

All of the devices operate with a single +5 V or –5.2 V supply.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

INPUT

DATA

DET

FUNCTIONAL BLOCK DIAGRAM

COMPENSATING

RETIMING

DEVICE

ZERO

Phase-Locked Loop

AD800/AD802

FILTER

LOOP

VCO

Fax: 617/326-8703

RETIMED

DATA

OUTPUT

RECOVERED

CLOCK

OUTPUT

FRAC

OUTPUT

Related parts for AD800-52BRZ

AD800-52BRZ Summary of contents

Page 1

... The VCO provides a clock output within 20% of the device center frequency in the absence of input data. The AD800 and AD802 exhibit virtually no pattern jitter, due to the performance of the patented phase detector. Total loop jitter is 20 peak-to-peak. Jitter bandwidth is dictated by mask programmable fractional loop bandwidth. The AD800, used for data rates < ...

Page 2

... –2– GND Loop Damping MAX CC A MIN MAX AD800-52BR AD802-155KR/BR Min Typ Max Min Typ Max 51.84 155. –40 85 – 155 156 49 53 155 156 11.5 ...

Page 3

... Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . +175 C Storage Temperature Range . . . . . . . . . . . . – +150 C Lead Temperature Range (Soldering 60 sec +300 C ESD Rating AD800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V AD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...

Page 4

... Bit Error Rate vs. Signal-to-Noise Ratio The AD800 and AD802 were designed to operate with standard ECL signal levels at the data input. Although not recom- mended, smaller input signals are tolerable. Figure 8, 14, and ...

Page 5

... Figure 4. AD800-45 Jitter vs. Temperature 100 100 1E-1 5E-2 3E-2 2E-2 1E-2 1E-3 1E-4 1E-5 1E-7 1E-9 1E-11 0.20 0.25 0.30 Figure 8. AD800-45 Bit Error Rate vs. Input Jitter –5– – AD800/AD802 – TEMPERATURE – C AD800-45 DS-3 MASK JITTER FREQUENCY – Hz Figure 6 ...

Page 6

... Figure 10. AD800-52 Jitter vs. Temperature 100 100 10 1E-1 5E-2 3E-2 2E-2 1E-2 1E-3 1E-4 1E-5 1E-6 1E-8 1E-10 0.20 0.25 0.30 Figure 14. AD800-52 Bit Error Rate vs. Input Jitter –6– – TEMPERATURE – C AD800-52 OC-1 MASK JITTER FREQUENCY – Hz Figure 12. AD800-52 Jitter Tolerance 80 ...

Page 7

... Figure 20. AD802-155 Bit Error Rate vs. Input Jitter to V MAX –7– AD800/AD802 – TEMPERATURE – C AD802-155 CCITT G.958 STM1 TYPE A MASK JITTER FREQUENCY – Hz Figure 18. AD802-155 Jitter Tolerance ...

Page 8

... The jitter bandwidths of the AD800-45 and AD800-52 are 0.1% of the respective center frequencies. The jitter bandwidth of the AD800 or the AD802 is mask programmable from 0.01 the center frequency. A device with a very low loop bandwidth (0.01% of the center frequency) could effectively filter (clean up) a jittery timing reference ...

Page 9

... F 2.5 TO DEVICE 0.1 F 2.0 BEAD WITH TWO LOOPS 1.5 TO DEVICE 0.1 F 1.0 BEAD WITH TWO LOOPS 0.5 TO DEVICE 0 Figure 24. AD802-155 Output Jitter vs. Supply Noise (PECL Configuration) –9– AD800/AD802 5.0V C17 0.1 FRAC FRAC R23 R22 130 10H116 R24 80 130 11 ...

Page 10

... ASUBST 2 Z1 AD800/802 –5.2V Description Resistor, 100 , 1% Resistor, 154 , 1% Resistor, 80 Resistor, 130 , 1% Resistor, 274 , 1% Capacitor, Loop Damping (See Specifications Page) Capacitor Tantalum Capacitor, 0.1 F, Ceramic Chip AD800/AD802 10H116, ECL Line Receiver –10– AD802-155 PINS 8, 13, PINS 10, 15, 18 PIN 3 –5.2V —5.2V ...

Page 11

... Figure 27. Negative Supply Configuration: Component Side (Top Layer) Figure 28. Negative Supply Configuration: Solder Side REV. B Figure 29. Positive Supply Configuration: Component Side (Top Layer) Figure 30. Positive Supply Configuration: Solder Side –11– AD800/AD802 ...

Page 12

... AD800/AD802 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Pin Small Outline IC Package (R-20) 0.512 (13.00) 0.496 (12.60 0.300 (7.60) 0.292 (7.40 0.50 (1.27) 0.019 (0.48) BSC 0.014 (0.36) 0.011 (0.28) 0.004 (0.10) 0.015 (0.38) 0.050 (1.27) ...

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