CY7B991-7JXC Cypress Semiconductor Corp, CY7B991-7JXC Datasheet - Page 16
![IC CLK BUFF SKEW 8OUT 32PLCC](/photos/6/51/65138/428-32-plcc_sml.jpg)
CY7B991-7JXC
Manufacturer Part Number
CY7B991-7JXC
Description
IC CLK BUFF SKEW 8OUT 32PLCC
Manufacturer
Cypress Semiconductor Corp
Type
Buffer/Driverr
Series
RoboClock™r
Specifications of CY7B991-7JXC
Number Of Circuits
1
Package / Case
32-PLCC
Ratio - Input:output
8:8
Differential - Input:output
Yes/Yes
Input
3-State, TTL
Output
TTL
Frequency - Max
80MHz
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
80MHz
Output Frequency Range
3.75 MHz to 80 MHz
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Clock Ic Type
Clock Buffer
Frequency
80MHz
No. Of Outputs
8
Supply Current
85mA
Supply Voltage Range
4.5V To 5.5V
Digital Ic Case Style
LCC
No. Of Pins
32
Rohs Compliant
Yes
Number Of Elements
1
Operating Supply Voltage (typ)
5V
Operating Temp Range
0C to 70C
Package Type
PLCC
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Pin Count
32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-1717-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7B991-7JXC
Manufacturer:
CY
Quantity:
7
Company:
Part Number:
CY7B991-7JXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7B991-7JXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Figure 10
of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire
delay) necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumu-
lates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers
in series.
Document Number: 38-07138 Rev. *I
SYSTEM
CLOCK
shows the CY7B991 and 992 connected in series to construct a zero skew clock distribution tree between boards. Delays
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Figure 10. Board-to-Board Clock Distribution
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
L4
L1
L2
L3
Z
0
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Z
Z
Z
0
0
0
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
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CY7B991
CY7B992
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