CY7B991-2JXC Cypress Semiconductor Corp, CY7B991-2JXC Datasheet - Page 10
![IC CLK BUFF SKEW 8OUT 32PLCC](/photos/6/51/65138/428-32-plcc_sml.jpg)
CY7B991-2JXC
Manufacturer Part Number
CY7B991-2JXC
Description
IC CLK BUFF SKEW 8OUT 32PLCC
Manufacturer
Cypress Semiconductor Corp
Type
Buffer/Driverr
Series
RoboClock™r
Datasheet
1.CY7B991-7JXC.pdf
(20 pages)
Specifications of CY7B991-2JXC
Number Of Circuits
1
Package / Case
32-PLCC
Ratio - Input:output
8:8
Differential - Input:output
Yes/Yes
Input
3-State, TTL
Output
TTL
Frequency - Max
80MHz
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
80MHz
Output Frequency Range
3.75 MHz to 80 MHz
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2241-5
CY7B991-2JXC
CY7B991-2JXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7B991-2JXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7B991-2JXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Characteristics
Over the Operating Range
Document Number: 38-07138 Rev. *E
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOM
RPWH
RPWL
U
SKEWPR
SKEW0
SKEW1
SKEW2
SKEW3
SKEW4
DEV
PD
ODCV
PWH
PWL
ORISE
OFALL
LOCK
JR
Parameter
Operating Clock
Frequency in MHz
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched-Pair Skew
(XQ0, XQ1)
Zero Output Skew (All Outputs)
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)
Device-to-Device Skew
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation
Output HIGH Time Deviation from 50%
Output LOW Time Deviation from 50%
Output Rise Time
Output Fall Time
PLL Lock Time
Cycle-to-Cycle Output
Jitter
[2, 13]
[16, 17]
(continued)
[16, 19]
[16, 19]
[26]
Description
[16, 19]
[23, 25]
[16, 19]
[23, 25]
[14, 21]
FS = LOW
FS = MID
FS = HIGH
RMS
Peak-to-Peak
[22]
[16, 18]
[14]
[1, 2]
[1, 2]
[1, 2 , 3]
[23, 24]
[23, 24]
[14]
–0.5
–1.0
0.15
0.15
Min
5.0
5.0
15
25
40
CY7B991–5
0.25
Typ
0.1
0.6
0.5
0.5
0.5
0.0
0.0
1.0
1.0
+0.5
+1.0
Max
0.25
1.25
200
0.5
0.7
1.0
0.7
1.0
2.5
1.5
1.5
0.5
30
50
80
25
3
See
–0.5
–1.2
Min
Table 2
5.0
5.0
0.5
0.5
15
25
40
CY7B992–5
0.25
Typ
0.1
0.6
0.6
0.5
0.6
0.0
0.0
2.0
2.0
80
Max
0.25
1.25
+0.5
+1.2
200
0.5
0.7
1.5
0.7
1.7
4.0
4.0
3.5
3.5
0.5
30
50
25
[15]
CY7B991
CY7B992
Page 10 of 20
MHz
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
[+] Feedback