PI6C182HE Pericom Semiconductor, PI6C182HE Datasheet - Page 5

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PI6C182HE

Manufacturer Part Number
PI6C182HE
Description
IC 1:10 CLOCK BUFFER 28-SSOP
Manufacturer
Pericom Semiconductor
Type
Fanout Buffer (Distribution)r
Datasheet

Specifications of PI6C182HE

Number Of Circuits
1
Ratio - Input:output
1:10
Differential - Input:output
No/No
Input
TTL
Output
TTL
Frequency - Max
110MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Frequency-max
110MHz
Number Of Outputs
10
Operating Supply Voltage (max)
3.465V
Operating Temp Range
0C to 70C
Propagation Delay Time
8ns
Operating Supply Voltage (min)
3.135V
Mounting
Surface Mount
Pin Count
28
Operating Supply Voltage (typ)
3.3V
Package Type
SSOP
Input Frequency
110MHz
Duty Cycle
55%
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI6C182HE
Manufacturer:
PER
Quantity:
116
Minimum and Maximum Expected
Capacitive Loads
Notes:
1.
2.
3.
SDRAM
Clock
Maximum rise/fall times are guaranteed at maximum specifi ed
load.
Minimum rise/fall times are guaranteed at minimum specifi ed
load.
Rise/fall times are specifi ed with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
08-0298
Min.
20
Max.
30
Waveform
Interface
Clocking
Input
Waveform
(TTL)
3.3V
Units
Output
pF
2.4
1.5
0.4
SDRAM DIMM
Specifi caion
t plh
(1,2,3)
t SDRISE
Notes
Figure 1. Clock Waveforms
1.5V
tSDKH
Output
Buffer
1.5V
5
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over
4. Position clock signals away from signals that go to any cables
t SDFALL
tSDKP
the respective clock pins. Typical value for CI is 10pF. Series
resistor value can be increased to reduce EMI provided that
the rise and fall time are still within the specifi ed values.
a continuous power plane. Avoid routing clock traces from
plane to plane (refer to rule #2).
or any external connectors.
Test Load
tSDKL
Test
Point
1.5V
1.5V
Precision 1-to-10 Clock Buffer
t phl
PI6C182, PI6C182A
PS8165G
11/13/08

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