MAX9316EWP Maxim Integrated Products, MAX9316EWP Datasheet - Page 4

• Manufacturer Part Number: MAX9316EWP
• Description: IC DRIVER CLOCK/DATA 1:5 20SOIC
• Manufacturer: Maxim Integrated Products
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of MAX9316EWP

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: HSTL, LVECL, LVPECL
• Output: LVECL, LVPECL
• Frequency - Max: 1.5GHz
• Voltage - Supply: 3 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Frequency-max: 1.5GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver
AC ELECTRICAL CHARACTERISTICS
(V
(20% to 80%), SEL = high or low, EN = low, V
otherwise noted. Typical values are at V
4
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at T
Note 4: Use V
Note 5: All pins are open except V
Note 6: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 7: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 8: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 9: Device jitter added to a jitter-free input signal.
PARAMETER
CLK to Q_ Delay
(Differential)
SCLK to Q_ Delay
Output-to-Output
Skew (Note 7)
Part-to-Part Skew
(Note 8)
Added Random
Jitter (Note 9)
Added
Deterministic Jitter
(Note 9)
Switching
Frequency
Output Rise/Fall
Time (20% to 80%)
CC
_______________________________________________________________________________________
- V
EE
= +3.0V to +3.8V, outputs are loaded with 50Ω ±1% to V
BB
only for inputs that are on the same device as the V
SYMBOL
t
t
t
t
PLHD1
PLHD3
t
PHLD1
PHLD3
t
SKOO
t
f
SKPP
MAX
R
t
t
RJ
DJ
, t
F
,
,
Figure 2
V
V
Figure 3
f
1.5Gbps 2E
PRBS pattern
( V
≥ 400m V ,
Figure 2
Figure 2
IN
CC
IL
IH
OH
CONDITIONS
= 1.5GHz clock
= V
= V
and V
CC
- V
CC
CC
- V
OL
EE
- 1.55V,
)
EE
- 1.09V,
IHD
23
.
-1
= +3.3V.) (Notes 1, 6)
= V
A
= +25°C and guaranteed by design over the full operating temperature range.
EE
+ 1.2V to V
MIN
290
290
1.5
80
-40°C
TYP
0.8
50
5
CC
CC
BB
, V
- 2V, input frequency = 1.5GHz, input transition time = 125ps
MAX
reference.
400
400
110
120
ILD
1.2
30
70
= V
MIN
EE
310
310
1.5
90
to V
+25°C
CC
TYP
0.8
20
50
- 0.15V, V
MAX
440
440
130
130
1.2
40
70
IHD
MIN
300
300
1.5
90
- V
ILD
+85°C
TYP
= 0.15V to 3V, unless
0.8
20
50
MAX
520
520
220
145
1.2
50
70
p s
ps (p-p)
UNITS
GHz
ps
ps
ps
ps
ps
( RM S )