MAX9316EWP Maxim Integrated Products, MAX9316EWP Datasheet - Page 7

• Manufacturer Part Number: MAX9316EWP
• Description: IC DRIVER CLOCK/DATA 1:5 20SOIC
• Manufacturer: Maxim Integrated Products
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of MAX9316EWP

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: HSTL, LVECL, LVPECL
• Output: LVECL, LVPECL
• Frequency - Max: 1.5GHz
• Voltage - Supply: 3 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Frequency-max: 1.5GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ed), allowing high-performance clock or data distribu-
tion in systems with a nominal +3.3V supply. For inter-
facing to differential LVECL, the V
-3.8V (with V
enced to V
depending on the level of the V
connected to a positive supply and V
ground, the outputs are LVPECL. The outputs are
LVECL when V
connected to a negative supply.
When the inputs are open, the internal bias resistors set
the inputs to low state. The inverting input (CLK) is
biased with a 75kΩ pullup to V
to V
ended input (SCLK) are each biased with a 75kΩ pull-
down to V
each biased with a 60kΩ pulldown to V
The maximum magnitude of the differential signal applied
to the differential clock input is 3.0V. This limit also
applies to the difference between any reference voltage
input and a single-ended input. Specifications for the high
and low voltages of a differential input (V
and the differential input voltage (V
simultaneously.
The differential clock input can be configured to accept
a single-ended input. This is accomplished by connect-
ing the on-chip reference voltage, V
or noninverting input of the differential input as a refer-
ence. For example, the differential CLK, CLK input is
converted to a noninverting, single-ended input by con-
necting V
input signal to CLK. Similarly, an inverting configuration
is obtained by connecting V
the single-ended input to CLK. With a differential input
configured as single ended (using V
ended input can be driven to V
single-ended LVPECL/LVECL signal. Note that the sin-
gle-ended input must be least V
ential input of at least 95mV to switch the outputs to the
V
Characteristics table.
When using the V
0.01µF ceramic capacitor to V
is not used, leave it open. The V
source or sink 0.5mA. Use V
on the same device as the V
OH
EE
and V
. The noninverting inputs (CLK) and the single-
BB
EE
CC
Single-Ended Clock Input and V
OL
. The single-ended EN and SEL inputs are
to CLK and connecting the single-ended
CC
and are considered LVPECL or LVECL,
CC
levels specified in the DC Electrical
Differential Clock Input Limits
grounded). Output levels are refer-
BB
_______________________________________________________________________________________
is connected to ground and V
reference output, bypass it with a
BB
1:5 Differential LVPECL/LVECL/HSTL
BB
BB
Input Bias Resistors
CC
CC
reference.
to CLK and connecting
only for an input that is
CC
BB
CC
. If the V
and a 75kΩ pulldown
EE
BB
BB
±95mV or a differ-
and V
supply. With V
IHD
range is -3.0V to
EE
EE
, to the inverting
BB
reference can
.
IHD
- V
), the single-
connected to
BB
EE
ILD
and V
reference
or with a
) apply
EE
ILD
BB
CC
is
)
Bypass V
ceramic 0.1µF and 0.01µF capacitors in parallel as
close to the device as possible, with the 0.01µF capaci-
tor closest to the device. Use multiple parallel vias to
minimize parasitic inductance. When using the V
erence output, bypass it with a 0.01µF ceramic capaci-
tor to V
left open).
Input and output trace characteristics affect the perfor-
mance of the MAX9316. Connect input and output sig-
nals with 50Ω characteristic impedance traces.
Minimize the number of vias to prevent impedance dis-
continuities. Reduce reflections by maintaining the 50Ω
characteristic impedance through cables and connec-
tors. Reduce skew within a differential pair by matching
the electrical length of the traces.
Terminate outputs with 50Ω to V
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if Q0 is used as a single-ended
output, terminate both Q0 and Q0.
TRANSISTOR COUNT: 616
PROCESS: Bipolar
Clock and Data Driver
CC
CC
(if the V
to V
Applications Information
EE
Controlled-Impedance Traces
BB
with high-frequency surface-mount
reference is not used, it can be
Chip Information
Output Termination
Supply Bypassing
CC
- 2V or use an
BB
ref-
7