MC100EP210SMNG ON Semiconductor, MC100EP210SMNG Datasheet - Page 2

• Manufacturer Part Number: MC100EP210SMNG
• Description: IC CLOCK DRIVER LVDS DUAL 32-QFN
• Manufacturer: ON Semiconductor
• Series: 100EPr
• Type: Fanout Buffer (Distribution)r

Specifications of MC100EP210SMNG

• Number Of Circuits: 2
• Ratio - Input:output: 1:5
• Differential - Input:output: Yes/Yes
• Input: LVDS, LVPECL
• Output: LVDS
• Frequency - Max: 1GHz
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TFQFN Exposed Pad
• Frequency-max: 1GHz
• Number Of Outputs: 20
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: -40C to 85C
• Propagation Delay Time: 0.675ns
• Operating Supply Voltage (min): 2.375V
• Mounting: Surface Mount
• Pin Count: 32
• Operating Supply Voltage (typ): 2.5V
• Package Type: QFN EP
• Input Frequency: >1000MHz
• Operating Temperature Classification: Industrial
• Clock Ic Type: Clock Driver
• Frequency: 1GHz
• No. Of Outputs: 5
• Ic Output Type: LVDS
• Supply Current: 150mA
• Supply Voltage Range: 2.375V To 2.625V
• Digital Ic Case Style: QFN
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Qa2
Qa2
Qa1
Qa1
Qa0
Qa0
V
V
CC
CC
Warning: All V
to Power Supply to guarantee proper operation.
Figure 1. 32−Lead LQFP Pinout (Top View)
25
26
27
28
29
30
31
32
CLKa
CLKa
Qa3 Qa3
V
24
1
EE
50 W
CC
VTA
23
2
and V
VTA
Qa4
22
MC100EP210S
*Under open or floating conditions with input pins converging to a common termination
3
Table 1. PIN DESCRIPTION
Qn0:4, Qn0:4
VTA
VTB
V
V
EP for QFN−32,
only
CLKn, CLKn
bias voltage the device is susceptible to auto oscillation.
PIN
CC
EE
EE
50 W
Qa4
21
4
pins must be externally connected
VTB
Qb0
20
5
Qb0
19
6
Qb1
18
7
FUNCTION
LVDS, LVPECL CLK Inputs*
LVDS Outputs
50 W Termination Resistors
50 W Termination Resistors
Positive Supply
Ground
The Exposed Pad (EP) on the QFN−32 package bottom is
thermally connected to the die for improved heat transfer out
of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is electrically connected to V
Qb1
V
17
8
EE
Figure 2. Logic Diagram
16
15
14
13
12
11
10
Qa0
Qa0
Qa1
Qa1
Qa2
Qa2
Qa3
Qa3
Qa4
Qa4
9
http://onsemi.com
MC100EP210S
V
Qb2
Qb2
Qb3
Qb3
Qb4
Qb4
V
CC
CC
2
CLKb
CLKb
50 W
CLKa
CLKa
CLKb
CLKb
VTB
VTA
V
V
EE
EE
VTB
Figure 1. 32−Lead QFN Pinout (Top View)
1
2
3
4
5
6
7
8
V
V
50 W
32
CC
CC
9
Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 V
Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 V
10
31
MC100EP210S
30
11
12
29
EE
.
28
13
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qb3
Qb3
Qb4
Qb4
14
27
26
15
16
25
CC
CC
24
23
22
21
20
19
18
17
Qa3
Qa3
Qa4
Qa4
Qb0
Qb0
Qb1
Qb1