MC100EP809FA ON Semiconductor, MC100EP809FA Datasheet - Page 6

• Manufacturer Part Number: MC100EP809FA
• Description: IC DRVR CLK PECL-HSTL 1:9 32LQFP
• Manufacturer: ON Semiconductor
• Series: 100EPr
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of MC100EP809FA

• Number Of Circuits: 2
• Ratio - Input:output: 1:9
• Differential - Input:output: Yes/Yes
• Input: HSTL, LVDS, LVPECL
• Output: HSTL
• Frequency - Max: 750MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 750MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC100EP809FAOS

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
5. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to GND (Figure 7).
6. Skew is measured between outputs under identical transitions and conditions on any one device.
7. Device−to−Device skew for identical transitions and conditions.
8. V
9. OE Set Up Time is defined with respect to the rising edge of the clock. OE High−to−Low transition ensures outputs remain disabled during
Table 8. AC CHARACTERISTICS
Symbol
V
t
t
t
t
V
t
t
t
PLH
PHL
skew
JITTER
S
H
r
/t
Opp
PP
the next clock cycle. OE Low−to−High transition enables normal operation of the next input clock (Figure 9).
f
PP
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
is the Differential Input Voltage swing required to maintain AC characteristics listed herein.
Figure 4. Output Frequency (F
Differential Output Voltage f
(Figure 4)
Propagation Delay (Differential Configura-
tion)
Within−Device Skew (Note 6)
Device−to−Device Skew (Note 7)
Random Clock Jitter (Figure 4) (RMS)
Input Swing (Differential Configuration)
(Note 8) (Figure 5)
OE Set Up Time (Note 9)
OE Hold Time
Output Rise/Fall Time
(20% − 80%)
Characteristic
900
800
700
600
500
400
300
200
100
0
0
LVPECL_CLK to Q
HSTL_CLK to Q
V
f
f
100
out
out
out
CCI
< 100 MHz
< 500 MHz
< 750 MHz
= 3.0 V to 3.6 V; V
LVPECL
OUT
200
V
RMS JITTER
OPP
HSTL
) versus Output Voltage (V
300
Min
600
600
450
680
690
200
200
350
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0.5
0.5
400
CCO
FREQUENCY (MHz)
0°C
Typ
800
830
100
850
750
575
1.4
= 1.6 V to 2.0 V, GND = 0 V (Note 5)
15
500
6
Max
930
990
200
600
600
3.0
50
700
OPP
Min
600
600
450
700
700
200
200
350
0.5
0.5
) and Random Clock Jitter (t
800
25°C
Typ
850
750
575
820
850
100
450
1.4
15
900
1000
Max
950
200
600
3.0
50
1000
9
8
7
6
5
4
3
2
1
Min
600
600
450
780
790
200
200
350
0.5
0.5
85°C
Typ
850
750
575
920
950
100
1.4
15
JITTER
1070
1110
Max
200
600
3.0
50
)
Unit
mV
mV
mV
mV
ps
ps
ps
ps
ps
ns
ns
ps