ADF4154BRUZ Analog Devices Inc, ADF4154BRUZ Datasheet

no-image

ADF4154BRUZ

Manufacturer Part Number
ADF4154BRUZ
Description
IC FRAC-N FREQ SYNTH 16-TSSOP
Manufacturer
Analog Devices Inc
Type
Fractional N Synthesizer (RF)r
Datasheet

Specifications of ADF4154BRUZ

Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
4GHz
Divider/multiplier
No/Yes
Voltage - Supply
2.7 V ~ 3.3 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Frequency-max
4GHz
Pll Type
Frequency Synthesis
Frequency
4GHz
Supply Current
20mA
Supply Voltage Range
2.7V To 5.5V
Digital Ic Case Style
TSSOP
No. Of Pins
16
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF4154EBZ1 - BOARD EVALUATION FOR ADF4154EB1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADF4154BRUZ
Manufacturer:
AD
Quantity:
6 500
Part Number:
ADF4154BRUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
ADF4154BRUZ
Quantity:
320
Part Number:
ADF4154BRUZ-RL7
Manufacturer:
AD
Quantity:
49
FEATURES
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
Separate V
Programmable dual-modulus prescaler 4/5, 8/9
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with the ADF4110/ADF4111/
Programmable modulus on fractional-N synthesizer
Trade-off noise vs. spurious performance
Fast-lock mode with built-in timer
Loop filter design possible with ADIsimPLL™
APPLICATIONS
Base stations for mobile radio (WiMAX, PHS, GSM, PCS, DCS,
Wireless handsets (PMR, GSM, PCS, DCS, CDMA, WCDMA)
CATV equipment
Wireless LANs
Communications test equipment
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ADF4112/ADF4113, ADF4106,
CDMA, PMR, W-CDMA, supercell 3G)
P
allows extended tuning voltage
MUXOUT
CLOCK
REF
DATA
LE
IN
ADF4154
HIGH Z
ADF4153
REGISTER
DOUBLER
OUTPUT
24-BIT
DATA
MUX
×2
FUNCTIONAL BLOCK DIAGRAM
AGND
V
DGND
V
R
N
DD
DD
DIV
DIV
DGND
FRACTION
R COUNTER
Fractional-N Frequency Synthesizer
FAST-LOCK
INTERPOLATOR
REG
DETECT
SWITCH
LOCK
THIRD ORDER
FRACTIONAL
4-BIT
AV
Figure 1.
DD
DV
MODULUS
DD
REG
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The ADF4154 is a fractional-N frequency synthesizer that
implements local oscillators in the up conversion and down
conversion sections of wireless receivers and transmitters. It
consists of a low noise digital phase frequency detector (PFD),
a precision charge pump, and a programmable reference divider.
There is a Σ-Δ based fractional interpolator to allow programmable
fractional-N division. The INT, FRAC, and MOD registers define
an overall N-divider (N = (INT + (FRAC/MOD))). In addition,
the 4-bit reference counter (R-counter) allows selectable REF
frequencies at the PFD input. A complete phase-locked loop (PLL)
can be implemented if the synthesizer is used with an external
loop filter and a voltage-controlled oscillator (VCO).
A key feature of the ADF4154 is the fast-lock mode with a built-
in timer. The user can program a predetermined countdown
time value so that the PLL remains in wide bandwidth mode,
instead of the user having to control this time externally.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
V
P
SDV
+
FREQUENCY
DETECTOR
CPGND
PHASE
DD
INTEGER REG
N COUNTER
RFCP3 RFCP2 RFCP1
REFERENCE
CURRENT
CHARGE
SETTING
PUMP
R
SET
©2006 Analog Devices, Inc. All rights reserved.
CP
RF
RF
IN
IN
A
B
ADF4154
www.analog.com
IN

Related parts for ADF4154BRUZ

ADF4154BRUZ Summary of contents

Page 1

FEATURES RF bandwidth to 4 GHz 2 3.3 V power supply Separate V allows extended tuning voltage P Programmable dual-modulus prescaler 4/5, 8/9 Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with ...

Page 2

ADF4154 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Pin Function ...

Page 3

SPECIFICATIONS SDV = 2 3 referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C. Table 1. Parameter B Version RF CHARACTERISTICS (3 V) ...

Page 4

ADF4154 TIMING CHARACTERISTICS SDV = 2 3 referred to 50 Ω. Table 2. 1 Parameter Limit MIN MAX ...

Page 5

ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND GND Digital I/O Voltage to GND Analog ...

Page 6

ADF4154 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS SET CPGND MUXOUT 3 14 ADF4154 AGND TOP VIEW RF B DATA (Not to Scale CLK 6 ...

Page 7

TYPICAL PERFORMANCE CHARACTERISTICS Loop bandwidth = 20 kHz; reference = 250 MHz; VCO = Vari-L Company, Inc., VCO190-1750T; evaluation board = EVAL-ADF4154EB1; measurements taken with the Agilent E5500 phase noise measurement system. –30 20kHz LOOP BW, LOW NOISE MODE –40 ...

Page 8

ADF4154 –80 –85 –90 –95 –100 –105 –110 VALUE (kΩ) SET Figure 11. Phase Noise vs. R –90 –92 –94 –96 –98 –100 –102 –104 –60 –40 – TEMPERATURE (°C) Figure 12. ...

Page 9

CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 14. While the device is operating, usually SW1 and SW2 are closed switches and SW3 is open. When a power-down is initiated, SW3 is closed and SW1 ...

Page 10

ADF4154 MUXOUT AND LOCK DETECT The output multiplexer on the ADF4154 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 (see Table 8). Figure 18 shows the ...

Page 11

REGISTERS Table 6. Register Summary 9-BIT RF N VALUE DB23 DB22 DB21 DB20 DB19 DB18 DB17 FL1 MUXOUT DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 ...

Page 12

ADF4154 Table 7. N-Divider Register Map 9-BIT RF N VALUE (INT) DB23 DB22 DB21 DB20 DB19 DB18 DB17 FL1 ...

Page 13

Table 8. R-Divider Register Map MUXOUT DB23 DB22 DB21 DB18 DB20 DB19 LOAD CONTROL P1 PRESCALER 0 NORMAL OPERATION 0 4/5 1 LOAD FAST LOCK TIMER 1 8 MUXOUT 0 ...

Page 14

ADF4154 Table 9. Control Register Map RESYNC DB15 DB14 DB13 ...

Page 15

Table 10. Noise and Spur Register DB10 T9 DB9, DB8, DB7, DB6, DB2 00000 11100 11111 NOISE AND SPUR RESERVED MODE DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB10, DB5, DB4, DB3 0 ...

Page 16

ADF4154 REGISTER DEFINITIONS N-Divider Register, R0 The on-chip N-divider register is programmed by setting R0 [ [0, 0]. Table 7 shows the input data format for programming this register. 9-Bit RF N Value (INT) These nine bits control ...

Page 17

RF Charge Pump Three-State This bit (DB3) puts the charge pump into three-state mode when it is programmed to 1. For normal operation, it should be set Power-Down DB4 on the ADF4154 provides the programmable power-down mode. ...

Page 18

ADF4154 INITIALIZATION SEQUENCE The following initialization sequence should be followed after powering up the part: 1. Clear all test modes by writing all 0s to the noise and spur register. 2. Select the noise and spur mode required for the ...

Page 19

Using the fast-lock feature can achieve the same fast-lock time as the noise and spur register, but with the advantage of lower spurious signals ...

Page 20

ADF4154 In low spur mode (dither enabled), the repeat length is 21 extended to 2 cycles, regardless of the value of MOD, which makes the quantization error spectrum appear as broadband noise. This can degrade the in-band phase noise at ...

Page 21

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package (CP-20-1) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the ...

Page 22

... ADF4154BRU-REEL7 −40°C to +85°C ADF4154BRUZ 1 −40°C to +85°C 1 ADF4154BRUZ-RL −40°C to +85°C 1 ADF4154BRUZ-RL7 −40°C to +85°C ADF4154BCP −40°C to +85°C ADF4154BCP-REEL −40°C to +85°C ADF4154BCP-REEL7 −40°C to +85°C 1 ADF4154BCPZ −40°C to +85°C ...

Page 23

NOTES Rev Page ADF4154 ...

Page 24

ADF4154 NOTES 2 Purchase of licensed I C components of Analog Devices, Inc., or one of its sublicensed Associated Companies conveys a license for the purchaser under the 2 Philips I C Patent Rights to use these components in an ...

Related keywords