AD9571ACPZPEC Analog Devices Inc, AD9571ACPZPEC Datasheet
AD9571ACPZPEC
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AD9571ACPZPEC Summary of contents
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FEATURES Fully integrated VCO/PLL core 0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz 0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz Input crystal or clock frequency of 25 MHz Preset ...
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AD9571 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 PLL Characteristics ...................................................................... 3 LVDS Clock Output Jitter ............................................................ 4 LVPECL Clock Output Jitter ...
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SPECIFICATIONS PLL CHARACTERISTICS Typical (typ) is given for Table 1. Parameter PHASE NOISE CHARACTERISTICS PLL Noise (156.25 MHz LVDS Output kHz @ 10 kHz @ 100 kHz @ 1 MHz @ ...
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AD9571 Parameter PLL Noise (125 MHz LVPECL Output kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz PLL Noise (100 MHz LVPECL Output kHz @ 10 kHz @ 100 ...
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LVPECL CLOCK OUTPUT JITTER Typical (typ) is given for Table 3. Jitter Integration 125 MHz Bandwidth (Typ) 100 MHz 33.33 MHz = Off/On 12 kHz to 20 MHz 0.54 0.42/2.0 1.875 MHz to ...
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AD9571 CLOCK OUTPUTS Typical (typ) is given for V = 3.3 V ± 10 over full V and T (−40°C to +85°C) variation Table 6. Parameter LVPECL CLOCK OUTPUTS Output Frequency Output High Voltage (V ) ...
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CONTROL PINS Typical (typ) is given for V = 3.3 V ± 10 over full V and T (−40°C to +85°C) variation Table 8. Parameter Min INPUT CHARACTERISTICS REFSEL Pin Logic 1 Voltage 2.0 Logic 0 ...
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AD9571 TIMING DIAGRAMS DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential DIFFERENTIAL 80% LVDS 20 Figure 4. LVDS Timing, Differential Rev Page SINGLE-ENDED 80% CMOS 5pF ...
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ABSOLUTE MAXIMUM RATINGS Table 11. Parameter Rating VS to GND −0 +3.6 V REFCLK to GND −0 0.3 V BYPASSx to GND −0 0 GND −0.3 V ...
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AD9571 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES SHORT TO PIN 36 SHORT TO PIN 14. 3. NOTE THAT THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION AS WELL AS A THERMAL ENHANCEMENT. ...
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Pin No. Mnemonic FORCE_LOW The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be ...
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AD9571 TYPICAL PERFORMANCE CHARACTERISTICS Both 100 MHz and 125 MHz outputs enabled; 33.33 MHz output disabled. –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 7. 125 MHz Phase Noise –100 –110 –120 –130 –140 ...
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TERMINOLOGY Phase Jitter An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 degrees to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation ...
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AD9571 THEORY OF OPERATION REFSEL VS XTAL OSC 1 0 REFCLK FREQUENCY DETECTOR AD9571 Figure 11 shows a block diagram of the AD9571. The chip consists of a PLL core, which is configured to generate the specific clock frequencies required ...
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Table 15. FREQSEL Definition Frequency Available from Pin 19 and Pin 20 FREQSEL (MHZ) 0 125 1 100 NC 125 3.5mA OUT OUT 3.5mA Figure 12. LVDS Output Simplified Equivalent Circuit The simplified equivalent circuits of the LVDS and LVPECL ...
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AD9571 The value of the resistor is dependent on the board design and timing requirements (typically 10 Ω to 100 Ω is used). CMOS outputs are limited in terms of the capacitive load or trace length that they can drive. ...
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... AD9571ACPZLVD- −40°C to +85°C AD9571ACPZPEC 1, 3 −40°C to +85° AD9571ACPZPEC-R7 −40°C to +85° AD9571ACPZPEC-RL −40°C to +85° AD9571-EVALZ-LVD 1, 3 AD9571-EVALZ-PEC RoHS Compliant Part. 2 LVD indicates LVDS compliant, differential clock outputs. 3 PEC indicates LVPECL compliant, differential clock outputs. ...
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AD9571 NOTES Rev Page ...
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NOTES Rev Page AD9571 ...
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AD9571 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07499-0-8/09(0) Rev Page ...