ADF4193BCPZ Analog Devices Inc, ADF4193BCPZ Datasheet
ADF4193BCPZ
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ADF4193BCPZ Summary of contents
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FEATURES New, fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 μs with phase settled by 20 μs 0.5° rms phase error at 2 GHz RF output Digitally programmable output phase RF ...
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ADF4193 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ........................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. ...
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SPECIFICATIONS SDV = 3 V ± 10 referred to 50 Ω unless otherwise noted. A MIN MAX Table 1. Parameter B Version RF CHARACTERISTICS RF ...
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ADF4193 Parameter B Version Power-Down 10 DD SW1, SW2, and SW3 R (SW1 and SW2 SW3 75 ON NOISE CHARACTERISTICS ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter AV to GND SDV GND Digital I/O Voltage to GND Analog ...
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ADF4193 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CMR Common-Mode Reference Voltage for the Differential Amplifier’s Output Voltage Swing. Internally biased to three-fifths Differential Amplifier Output to Tune ...
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Pin No. Mnemonic Description 23 R Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at SET the R pin is 0.55 V. The relationship between I SET I = 0.25/R ...
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ADF4193 TYPICAL PERFORMANCE CHARACTERISTICS FREQ. UNIT GHz KEYWORD R PARAM TYPE S IMPEDANCE 50 DATA FORMAT MA FREQ. MAGS11 ANGS11 FREQ. 0.5 0.8897 –16.6691 2.3 0.6 0.87693 –19.9279 2.4 0.7 0.85834 –23.561 2.5 0.8 0.85044 –26.9578 2.6 0.9 0.83494 –30.8201 ...
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V TUNE 3 CP OUT OUT– DCS1800 Tx SETUP, 60kHz LOOP BW. 1 MEASURED ON EVAL-ADF4193-EB1 EVALUATION BOARD. TIMERS: ICP = 28, SW1/SW2, SW3 = 35. FREQUENCY LOCK IN WIDE BW MODE @ 4 μ s. ...
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ADF4193 1000 100 7nV 20kHz 10k 100k FREQUENCY (Hz) Figure 16. Voltage Noise Density Measured at the Differential Amplifier Output 100 SW3 90 +85°C SW1/ 80 SW2 +85°C +25°C 70 +25°C –40° –40°C ...
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THEORY OF OPERATION The ADF4193 is targeted at GSM base station requirements, specifically to eliminate the need for ping-pong solutions. It works based on fast lock, using a wide loop bandwidth during a frequency change and narrowing the loop bandwidth ...
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ADF4193 The value of MOD is chosen to give the desired channel step with the available reference frequency. Thereafter, program the INT and FRAC words for the desired RF output frequency. See the Worked Example section for more information. PFD ...
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START WRITE TO R0 ICP SW1/SW2 TIMEOUT TIMEOUT COUNTER COUNTER F ÷4 PFD CHARGE PUMP ENABLE LOGIC EN[64:1] Figure 25. Fast Lock Timeout Counters Differential Amplifier The internal, low noise, differential-to-single-ended amplifier is used to convert the differential charge pump ...
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ADF4193 REGISTER MAP 8-BIT RF INT VALUE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DBB DBB DBB 4-BIT RF R COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 ...
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FRAC/INT REGISTER (R0) 8-BIT RF INT VALUE DB23 DB22 DB21 DB20 DB19 DB18 DB17 R0, ...
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ADF4193 MOD/R REGISTER (R1) 4-BIT RF R COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 REF/2 0 DISABLE 1 ENABLE F2 PRESCALER F1 DOUBLER ENABLE 0 4/5 0 DOUBLER DISABLED 1 8/9 ...
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PHASE REGISTER (R2) DB15 DB14 DB13 0 P12 P11 P12 12-Bit Phase The phase word sets the seed value of the Σ-Δ modulator. It can be programmed to any integer ...
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ADF4193 FUNCTION REGISTER (R3) DB15 DB14 DB13 R3, the function register (C3, C2, C1 set respectively), only needs to be programmed during the initialization sequence (see Table 8). CPO GND When the CPO ...
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CHARGE PUMP REGISTER (R4) RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 Reserved Bits Bit DB23 to Bit DB14 are reserved and should be set to hex code 001 for normal operation. 9-Bit ...
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ADF4193 POWER-DOWN REGISTER (R5) R5, the power-down register (C3, C2, C1 set respectively) can be used to software power down the PLL and differential amplifier sections. After power is initially applied, there must be writes to ...
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MUX REGISTER (R6) SIGMA-DELTA AND LOCK DETECT MODES DB15 DB14 DB13 M13 M12 M11 M13 M12 M11 ALL OTHER STATES With C3, C2, and C1 set respectively, ...
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ADF4193 PROGRAMMING The ADF4193 can synthesize output frequencies with a channel step or resolution that is a fraction of the input reference frequency. For a given input reference frequency and a desired output frequency step, the first choice to make ...
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The 8:1 loop bandwidth switching ratio of the ADF4193 makes it possible to attenuate all spurs to sufficiently low levels for most applications. The final loop BW can be chosen to ensure that all spurs are far enough out of ...
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ADF4193 phase swing that occurs when the BW is reduced can be minimized. With dither off, the fractional spur pattern due to the SDM’s quantization noise also depends on the phase word the modulator is seeded with. Tables of optimized ...
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APPLICATIONS LOCAL OSCILLATOR FOR A GSM BASE STATION Figure 36 shows the ADF4193 being used with a VCO to produce the LO for a GSM1800 base station. For GSM, the REF signal can be any integer multiple of 13 MHz, ...
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ADF4193 ADI SimPLL Support The ADF4193 loop filter design is supported on ADI SimPLL v2.7 or later. Example files for popular applications are available for download from the applications section of the ADF4193 product page. + 10µF 100nF 100nF 15 ...
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INTERFACING The ADF4193 has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 24 bits that have been clocked into the input register on each rising ...
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... SEATING PLANE ORDERING GUIDE 1, 2 Model Temperature Range ADF4193BCPZ −40°C to +85°C ADF4193BCPZ-RL −40°C to +85°C ADF4193BCPZ-RL7 −40°C to +85°C ADF4193WCCPZ-RL7 −40°C to +105°C EVAL-ADF4193EBZ1 EVAL-ADF4193EBZ2 RoHS Compliant Part Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADF4193W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models ...