CY7B9910-5SXI Cypress Semiconductor Corp, CY7B9910-5SXI Datasheet
CY7B9910-5SXI
Specifications of CY7B9910-5SXI
Related parts for CY7B9910-5SXI
CY7B9910-5SXI Summary of contents
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... Jitter: <200 ps Peak to Peak, <25 ps RMS Functional Description The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low skew system clock distribution. These multiple output clock drivers optimize the timing of high performance computer systems. Each of the eight individual drivers can drive terminated transmission lines with impedances as low as 50Ω ...
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... PWR Ground. Test Mode The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 and CY7B9920 to operate as described in Block Diagram removable jumper to ground or be tied LOW through a 100Ω resistor. This enables an external tester to change the state of these pins. ...
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... CC Min ≤ V ≤ Max V /2 – 500 mV Min ≤ V ≤ Max 0 Max Max Max 0.4V –500 CC IN note 3 for variable definition. CY7B9910 CY7B9920 Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° 5V ± 10% – +85 C CY7B9920 Max Min Max Unit V V –0. ...
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... Tested initially and after any design or process changes that may affect these parameters. Parameter Description C Input Capacitance IN 5V R1=130 R1 R2= (Includes fixture and probe capacitance 7B9910–3 TTL AC Test Load (CY7B9910 R1=100 R2=100 (Includes fixture and probe capacitance 7B9910–5 CMOS AC Test Load (CY7B9920) Document Number: 38-07135 Rev. *E Test Conditions V ...
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... Applies to REF and FB inputs only. 11. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test conditions assume signal transition times less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. ...
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... Document Number: 38-07135 Rev. *E CY7B9910–7 Min Typ [ LOW 15 [ MID HIGH 40 5.0 5.0 [13, 14] 0.3 –0.7 0.0 [16] –1.2 0.0 0.15 1.5 0.15 1.5 [8] Peak to Peak [8] RMS CY7B9910 CY7B9920 CY7B9920–7 Max Min Typ Max Unit MHz [12 5.0 ns 5.0 ns 0.75 0.3 0.75 ns 1.5 1.5 ns +0.7 – ...
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... Figure 4. Zero Skew and Zero Delay Clock Driver FB SYSTEM REF CLOCK FS TEST Document Number: 38-07135 Rev. *E Figure 3. AC Timing Diagrams t t REF RPWL t RPWH t ODCV t ODCV t SKEW t SKEW REF CY7B9910 CY7B9920 t JR LOAD Z 0 LOAD Z 0 LOAD Z 0 LOAD Z 0 Page [+] Feedback ...
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... Figure 3 shows the CY7B9910/9920 connected in series to construct a zero skew clock distribution tree between boards. Cascaded clock buffers accumulates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. ...
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... CY7B9920–5SC [20] CY7B9920–5SCT [20] CY7B9920–5SI Pb-free 250 CY7B9910–2SXC CY7B9910–2SXCT 500 CY7B9910–5SXC CY7B9910–5SXCT CY7B9910–5SXI CY7B9910–5SXIT 750 CY7B9910–7SXC CY7B9910–7SXCT Package Diagram Figure 6. 24-Pin (300-Mil) Molded SOIC S13 PIN 0.291[7.391] 0.300[7.620 0.026[0.660] 0.032[0.812] 0.597[15.163] 0.615[15.621] ...
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... Document History Page Document Title: CY7B9910/CY7B9920 Low Skew Clock Buffer Document Number: 38-07135 Orig. of Submission Revision ECN Change ** 110244 SZV *A 1199925 DPF/AESA *B 1353343 AESA *C 2750166 TSAI *D 2761988 CXQ *E 2896073 CXQ Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office ...