EL4585CSZ Intersil, EL4585CSZ Datasheet - Page 10

IC PLL VIDEO GP 36MHZ 16-SOIC

EL4585CSZ

Manufacturer Part Number
EL4585CSZ
Description
IC PLL VIDEO GP 36MHZ 16-SOIC
Manufacturer
Intersil
Type
Phase Lock Loop (PLL)r
Datasheet

Specifications of EL4585CSZ

Pll
Yes
Input
Clock
Output
CMOS, TTL
Number Of Circuits
1
Ratio - Input:output
3:1
Differential - Input:output
No/No
Frequency - Max
36MHz
Divider/multiplier
Yes/No
Voltage - Supply
5V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Frequency-max
36MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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C
control from the oscillator, and V
device. C
maximum modulation capability. The frequency of oscillation
is given by Equation 4:
F
C
Choosing Loop Filter Components
The PLL, VCO, and loop filter can be described as:
Where:
It can be shown that for the loop filter shown in Equation 5:
C
Where ω
factor.
N
1. K
2. The loop bandwidth should be about H
3. N = 910x2 = 1820 from Table 1.
4. K
1
T
3
=
K
F(s) = loop filter impedance in V/A
K
N = Total internal or external divisor (see 3 below)
=
is to adjust the center frequency, C
=
=
d
VCO
frequency/20, and the damping ratio should be 1 for
optimum performance. For our example,
ω
for each volt applied at the control pin. It is assumed (but
---------------------- -
2π LC
------------------- -
F
F
= phase detector gain in A/rad
d
n
VCO
------------------------------------------------------------------------- -
(
K
----------------------- - C
Hsync
C
VCO
d
= 300µA/2πrad = 4.77e-5A/rad for the EL4585.
= 15.734kHz/20=787 Hz≈5000 rad/S.
1
1
K
n
= VCO gain in rad/s/V
C
2
VCO
represents how much the VCO frequency changes
= loop filter bandwidth, and ζ = loop filter damping
2
2
n
T
should be much larger than C
)
FIGURE 10. COLPITTS OSCILLATOR
=
+
,
C
--------------------------- -
15.73426k
(
28.636M
C
1
4
C
1
C
=
2
C
V
C
------ - R
10
)
v
3
+
,
(
C
=
3
1
C
1820
=
10
V
----------------------- -
K
)
2Nζω
d
1
K
=
VCO
is the primary control
910x2
n
2
DC isolates the
V
SYNC
so that V
1
(EQ. 6)
has
(EQ. 4)
(EQ. 5)
EL4585
C
C
R
Lock Time
Let T = R
does lock time. Decreasing T decreases damping and
speeds up loop response, but increases overshoot and thus
increases the number of hunting oscillations before lock.
Critical damping (ζ=1) occurs at minimum lock time.
Because decreased damping also decreases loop stability, it
is sometimes desirable to design slightly overdamped (ζ>1),
trading lock time for increased stability.
5. Now we can solve for C
6. Notice R
3
4
3
=
=
=
probably is not) linear about the lock point (2.5V). Its
value depends on the VCO configuration and the varactor
transfer function C
bias control voltage, and C
Since F(V
VCO and measure K
such measurement are shown below. The slope of the
curve is determined by linear regression techniques and
equals K
We choose R
should be large, around 100k, and can be adjusted to
compensate for any static phase error Tθ at lock, but if
made too large, will slow loop response. If R
smaller, Tθ (see “Timing Diagrams” on page 5) increases,
and if R
lock, |Tθ| < 50ns. C
frequency noise from the charge pump. The effect these
components have on-time to lock is illustrated in
Figure 12.
K
----------------------- -
C
------ -
----------------------- -
K
10
2Nζω
d
d
3
K
K
=
3
VCO
VCO
C
2
n
0.001μF
2
2
3
2
VCO
increases, Tθ decreases. For LDET to be low at
. As T increases, damping increases, but so
C
FIGURE 11. FOSC vs VC, LC VCO
has little effect on the loop filter design. R
=
=
) is nonlinear, it is probably best to build the
(
----------------------------------------------------- -
2 ( ) 1820
----------------------------------------------------- -
(
. For our example, K
3
4.77e 5
4.77e 5
= 43kΩ for convenience.
(
(
1820
V
4
= F(V
VCO
) 5000
is used mainly to attenuate high
) 1 ( ) 5000
(
) 9.06e6
) 9.06e6
(
(
3
, C
(
about 2.5V. The results of one
C
V
)
), where V
4
2
is varactor capacitance.
, and R
)
)
)
=
=
VCO
0.01μF
42.1kΩ
3
C
in Equation 7:
= 9.06 Mrad/s/V.
is the reverse
September 3, 2009
2
is made
FN7175.4
(EQ. 7)
2

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