FS6377-01IG-XTD ON Semiconductor, FS6377-01IG-XTD Datasheet - Page 23
![IC CLOCK GEN 3-PLL PROGR 16-SOIC](/photos/6/55/65519/fs6377-01ig-xtd_sml.jpg)
FS6377-01IG-XTD
Manufacturer Part Number
FS6377-01IG-XTD
Description
IC CLOCK GEN 3-PLL PROGR 16-SOIC
Manufacturer
ON Semiconductor
Type
PLL Clock Generatorr
Datasheet
1.FS6377-01G-XTD.pdf
(24 pages)
Specifications of FS6377-01IG-XTD
Pll
Yes
Input
Crystal
Output
CMOS
Number Of Circuits
1
Ratio - Input:output
1:4
Differential - Input:output
No/No
Frequency - Max
230MHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Frequency-max
230MHz
Number Of Elements
3
Pll Input Freq (min)
5MHz
Pll Input Freq (max)
27MHz
Operating Supply Voltage (typ)
3.3/5V
Operating Temp Range
-40C to 85C
Package Type
SOIC
Output Frequency Range
0.8 to 150MHz
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Pin Count
16
Mounting Style
SMD/SMT
Number Of Outputs
1
Operating Temperature Range
0 C to + 70 C
Supply Current
43 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
766-1027
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FS6377-01IG-XTD
Manufacturer:
ON Semiconductor
Quantity:
135
Company:
Part Number:
FS6377-01IG-XTD
Manufacturer:
Exar
Quantity:
40
FS6377
Figure 15: PLL Screen
For a 100MHz output, the VCO should ideally operate at a higher frequency, and the reference and feedback dividers should be as
small as possible. In this example, highlight Solution #7. Notice the VCO operates at 200MHz with a post divider of two to obtain an
optimal 50 percent duty cycle.
Now choose which mux and post divider to use (that is, choose an output pin for the 100MHz output). Selecting A places the PostDiv
value in Solution #7 into post divider A and switches mux A to take the output of PLL A.
The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in Solution #7. Also note that
mux A has been switched to PLL A and the post divider A has the chosen 100MHz output displayed.
Repeat the steps for PLL B.
PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both mux C and mux D are also affected
by the logic level on the SEL_CD pin, as are the post dividers C and D.
Figure 16: Post Divider Menu
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