fs6377 AMI Semiconductor, Inc., fs6377 Datasheet

Page 1

... Accepts 5MHz to 27MHz crystal resonators • Commercial and industrial temperature ranges offered 2.0 Description The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three 2 I C-programmable phase locked loops (PLLs) feeding four programmable muxes and post dividers provide a high degree of flexibility. ...

Page 2

... FS6377-01x Programmable 3-PLL Clock Generator IC Table 1: Pin Descriptions Pin Type Name Description SDA Serial interface data input/output SEL_CD Selects one of two PLL C, mux D/C and post divider C/D combinations Power-down input 4 P VSS Ground 5 AI XIN Crystal oscillator input ...

Page 3

... FS6377-01x Programmable 3-PLL Clock Generator IC 3.0 Functional Block Description 3.1 Phase Locked Loops (PLLs) Each of the three on-chip PLLs is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired frequency by a ratio of integers. This frequency multiplication is exact. As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), and a feedback divider ...

Page 4

... FS6377-01x Programmable 3-PLL Clock Generator IC For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to achieve a desired input- frequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large. ...

Page 5

... SEL_CD pin. 4.0 Device Operation The FS6377 powers up with all internal registers cleared to zero, delivering the crystal frequency to all outputs. For operation to occur, the registers must be loaded in a most significant-bit (MSB) to least-significant-bit (LSB) order. The register mapping of the FS6377 is ...

Page 6

... FS6377-01x Programmable 3-PLL Clock Generator IC 4.3 Oscillator Overdrive For applications where an external reference clock is provided (and the crystal oscillator is not required), the reference clock should be connected to XOUT and XIN should be left unconnected (float). For best results, make sure the reference clock signal is as jitter-free as possible, can drive a 40pF load with fast rise and fall times and can swing rail-to-rail. If the reference clock is not a rail-to-rail signal, the reference must be AC coupled to XOUT through a 0.01µ ...

Page 7

... FS6377-01x Programmable 3-PLL Clock Generator IC overwritten to the device after the first sixteen bytes will overflow into the first register, then the second, and so on first-in, first- overwritten fashion. 5.1.5. Acknowledge When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the acknowledge bit ...

Page 8

... FS6377-01x Programmable 3-PLL Clock Generator IC 5.2.4. Sequential Register Write Procedure Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the random register write if several registers must be written. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address ...

Page 9

... FS6377-01x Programmable 3-PLL Clock Generator IC – Oct., 2007 – Rev. 3.0 AMI Semiconductor www.amis.com Specifications subject to change without notice Figure 5: Random Register Write Procedure Figure 6: Random Register Read Procedure Figure 7: Sequential Register Write Procedure Figure 8: Sequential Register Read Procedure 9 Data Sheet ...

Page 10

... FS6377-01x Programmable 3-PLL Clock Generator IC 6.0 Programming Information Table 3: Register Map Address BIT 7 BIT 6 MUX_D2[1:0] Byte 15 (selected via SEL_CD = 1 (selected via SEL_CD = 1) POST_D2[3:0] Byte 14 (selected via SEL_CD = 1) POST_D1[3:0] Byte 13 (selected via SEL_CD = 0) POST_B[3:0] Byte 12 MUX_D1[1:0] Reserved (0) Byte 11 (selected via SEL_CD = 0) FBKDIV_C2[7:3] M-Counter ...

Page 11

... FS6377-01x Programmable 3-PLL Clock Generator IC 6.2 Power-Down All power-down functions are controlled by enable bits. The bits select which portions of the device to power-down when the PD input is asserted. Table 4: Power-Down Bits Name Description Power-Down PLL A Bit = 0 Power on PDPLL_A (Bit 21) Bit = 1 Power off Power-Down PLL B ...

Page 12

... FS6377-01x Programmable 3-PLL Clock Generator IC Table 6: Divider Control Bits Name Description POST_A[3:0] POST divider A (see Table 7) (Bits 99-96) POST_B[3:0] POST divider B (see Table 7) (Bits 103-100) POST divider C1 (see Table 7) POST_C1[3:0] (Bits 107-104) selected when the SEL_CD pin = 0 POST divider C2 (see Table 7) POST_C2[3:0] ...

Page 13

... FS6377-01x Programmable 3-PLL Clock Generator IC Table 8: PLL Tuning Bits Name Description Loop Filter Time Constant A Bit = 0 Short time constant: 7µs LFTC_A (Bit 20) Bit = 1 Long time constant: 20µs Loop Filter Time Constant B selected when the SEL_CD pin = 0 Bit = 0 Short time constant: 7µs ...

Page 14

... FS6377-01x Programmable 3-PLL Clock Generator IC Table 9: Mux Select Bits Name Description Mux A Frequency Select Bit 23 Bit MUX_A[1: (Bits 23-22 Mux B Frequency Select Bit 47 Bit MUX_B[1: (Bits 47-46 Mux C1 Frequency Select selected when the SEL_CD pin = 0 ...

Page 15

... FS6377-01x Programmable 3-PLL Clock Generator IC 7.0 Electrical Specifications Table 10: Absolute Maximum Ratings Parameter Supply voltage ground) SS Input voltage, dc Output voltage, dc Input clamp current < > Output clamp current < > Storage temperature range (non-condensing) Ambient temperature range, under bias ...

Page 16

... FS6377-01x Programmable 3-PLL Clock Generator IC Table 12: DC Electrical Specifications (continued) Mode and Frequency Select Inputs (ADDR, SEL_CD) High-level input voltage Low-level input voltage High-level input current Low-level input current (pull-up) Crystal Oscillator Feedback (XIN) Threshold bias voltage High-level input current Low-level input current ...

Page 17

... FS6377-01x Programmable 3-PLL Clock Generator IC – Oct., 2007 – Rev. 3.0 AMI Semiconductor www.amis.com Specifications subject to change without notice Figure 10: Dynamic Current vs. Output Frequency 17 Data Sheet ...

Page 18

... FS6377-01x Programmable 3-PLL Clock Generator IC Table 13: AC Timing Specifications Parameter Symbol Conditions/Descriptions Overall V Output frequency VCO frequency VCO V VCO gain* A VCO Loop filter time constant* LFTC bit = 0 LFTC bit = 1 Rise time Fall time Tristate enable delay* ...

Page 19

... FS6377-01x Programmable 3-PLL Clock Generator IC Table 13: AC Timing Specifications continued Clock Outputs (PLL_C clock via CLK_C pin) Approximate Duty cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period t On rising edges 500µs apart at 2.5V relative to an Jitter, long term (σ ...

Page 20

... FS6377-01x Programmable 3-PLL Clock Generator IC 8.0 Package Information – For Both ‘Green’ and ‘No-Green’ Table 15: 16-pin SOIC (0.150") Package Dimensions Dimensions Inches Millimeters Min. Max. Min. Max. A 0.061 0.068 1.55 1.73 A1 0.004 0.0098 0.102 0.249 A2 0.055 0.061 1.40 1.55 B 0.013 0.019 0.33 0.49 C 0.0075 0.0098 ...

Page 21

... Tube/Tray; -XTP = Tape & Reel 10.0 Demonstration Software Windows XP- (and earlier) based software is available from AMI Semiconductor that illustrates the capabilities of the FS6377 and aids in application development. Contact your local sales representative for more information. 10.1 Software Requirements • PC running MS Windows 95/98, 98 SE, ME, NT4, 2000, XP Home Edition Professional Edition • ...

Page 22

... FS6377-01x Programmable 3-PLL Clock Generator IC The FS6377 demo hardware is available on a limited basis for demonstration by an AMIS field applications engineer, but is no longer available for purchase. The opening screen is shown in Figure 14. 10.2.1. Example Programming Type a value for the crystal resonator frequency in MHz in the reference crystal box. This frequency provides the basis for all of the PLL calculations that follow. – ...

Page 23

... FS6377-01x Programmable 3-PLL Clock Generator IC Next, click on the PLL A box. A pop-up screen similar to Figure 15 should appear. Type in a desired output clock frequency in MHz, set the operating voltage (3.3V or 5V) and the desired maximum output frequency error. Pressing Calculate Solutions generates several possible divider and VCO-speed combinations. ...

Page 24

... FS6377-01x Programmable 3-PLL Clock Generator IC Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the post divider B as the output divider. Notice the post divider box has split in two (as shown in Figure 16). The post divider B box now shows that the divider is dependent on the setting of the SEL_CD pin for as long as mux B is the PLL C output ...

Page 25

... FS6377-01x Programmable 3-PLL Clock Generator IC 11.0 Company or Product Inquiries For more information about AMI Semiconductor’s products or services visit our Web site at http://www.amis.com. 12.0 Revision History Revision Date Modification 1.0 2004 Initial doc 2.0 2004 3.0 October 2007 Update format Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement ...