fs6377 AMI Semiconductor, Inc., fs6377 Datasheet - Page 19

• Manufacturer Part Number: fs6377
• Description: Fs6377-01g Programmable 3-pll Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

FS6377-01x Programmable 3-PLL Clock Generator IC
Table 13: AC Timing Specifications continued
Unless otherwise stated, V
nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3σ from typical.
Table 14: Serial Interface Timing Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T
represent nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3σ from typical.
Clock Outputs (PLL_C clock via CLK_C pin) Approximate
Duty cycle*
Jitter, long term (σy(τ))*
Jitter, period (peak-peak)*
Clock Outputs (Crystal Oscillator via CLK_D pin) Approximate
Duty cycle*
Jitter, long term (σy(τ))*
Jitter, period (peak-peak)*
Parameter
Clock frequency
Bus free time between STOP and
START
Set-up time, START (repeated)
Hold time, START
Set-up time, data input
Hold time, data input
Output data valid from clock
Rise time, data and clock
Fall time, data and clock
High time, clock
Low time, clock
Set-up time, STOP
AMI Semiconductor
www.amis.com
Specifications subject to change without notice
DD
– Oct., 2007 – Rev. 3.0
= 5.0V ± 10%, no load on any output, and ambient temperature range T
t
t
t
t
j(LT)
j(∆P)
j(LT)
j(∆P)
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
On rising edges 500µs apart at 2.5V relative to an
ideal clock, C
N
On rising edges 500µs apart at 2.5V relative to an
ideal clock, C
N
B = 60MHz, D = 14.318MHz)
From rising edge to the next rising edge at 2.5V,
C
N
From rising edge to the next rising edge at 2.5V,
C
N
B = 60MHz, D = 14.318MHz)
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
On rising edges 500µs apart at 2.5V relative to an
ideal clock, C
PLLs active
From rising edges to the next at 2.5V, C
f
B = 60MHz, C = 40MHz)
From rising edge to the next rising edge at 2.5V,
C
From rising edge to the next rising edge at 2.5V,
C
(A = 50MHz, B = 60MHz, C = 40MHz)
XIN
Symbol
f
t
t
t
t
t
t
t
t
t
t
T
SCL
BUF
su:STA
nd:STA
su:DAT
hd:DAT
AA
R
F
HI
LO
R
R
L
PX
L
PX
L
L
su:STO
= 15pF, f
= 15pF, f
= 15pF, f
= 15pF, f
= 63, N
= 63, N
= 14.318MHz, all other PLLs active (A = 50MHz,
= 50, no other PLLs active
= 50, all other PLLs active (A = 50MHz,
PX
PX
XIN
XIN
XIN
XIN
= 50, no other PLLs active
= 50, all other PLLs active (A = 50MHz,
L
L
L
= 14.318MHz, N
= 14.318MHz, N
= 14.318MHz, no other PLLs active
= 14.318MHz, all other PLLs active
= 15pF, f
= 15pF, f
= 15pF, f
Conditions/Description
SCL
SDA
SDA
Minimum delay to bridge undefined region of
the falling edge of SCL to avoid unintended
START or STOP
SDA, SCL
SDA, SCL
SCL
SCL
XIN
XIN
XIN
19
= 14.318MHz, N
= 14.318MHz, N
= 14.318MHz, no other
F
F
= 220, N
= 220, N
L
R
R
= 15pF,
= 63,
= 63,
F
F
= 220,
= 220,
A
= 0°C to 70°C. Parameters denoted with an asterisk (*) represent
14.318
14.318
14.318
14.318
14.318
A
100
100
100
40
40
= 0°C to 70°C. Parameters denoted with an asterisk (*)
45
45
Min.
Standard Mode
250
4.7
4.7
4.0
4.0
4.7
4.0
0
0
105
120
440
450
45
20
40
90
Max.
1000
55
55
100
300
3.5
Data Sheet
ps
ps
ps
ps
%
%
Units
kHz
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
µs