ADF4001BRU Analog Devices Inc, ADF4001BRU Datasheet - Page 14

• Manufacturer Part Number: ADF4001BRU
• Description: IC CLOCK GEN PLL 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator (RF)r

Specifications of ADF4001BRU

• Rohs Status: RoHS non-compliant
• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 200MHz
• Number Of Elements: 1
• Supply Current: 5.5mA
• Pll Input Freq (min): 5MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3/5V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Pin Count: 16
• For Use With: EVAL-ADF4001EBZ2 - BOARD EVAL FOR ADF4001
• Lead Free Status / RoHS Status: Not Compliant

ADF4001
COHERENT CLOCK GENERATION
When testing A/D converters, it is often advantageous to use a
coherent test system, that is, a system that ensures a specific
relationship between the A/D converter input signal and the
A/D converter sample rate. Thus, when doing an FFT on this
data, there is no longer any need to apply the window weighting
function. Figure 8 shows how the ADF4001 can be used to handle
all the possible combinations of the input signal frequency and
sampling rate. The first ADF4001 is phase locked to a VCO. The
output of the VCO is also fed into the N divider of the second
ADF4001. This results in both ADF4001s being coherent with
the REF
MUXOUT signal of the second ADF4001 is coherent with the f
frequency to the ADC. This is used as f
TRI-BAND CLOCK GENERATION CIRCUIT
In multiband applications, it is necessary to realize different
clocks from one master clock frequency. For example, GSM
uses a 13 MHz system clock, WCDMA uses 19.44 MHz, and
CDMA uses 19.2 MHz. The circuit in Figure 9 shows how to
use the ADF4001 to generate GSM, WCDMA, and CDMA
system clocks from a single 52 MHz master clock. The low RF
f
low as
clock frequencies can be realized using the formula
SHUTDOWN CIRCUIT
The circuit in Figure 10 shows how to shut down both the
ADF4001 and the accompanying VCO. The ADG702 switch
goes open circuit when a Logic 1 is applied to the IN input.
The low cost switch is available in both SOT-23 and micro
SOIC packages.
MIN
MODEL 1051
BRUEL &
KJAER
SQUARE
OUTPUT
OUTPUT
specification and the ability to program R and N values as
SINE
IN
1 makes the ADF4001 suitable for this. Other f
. Since the REF
REF
Figure 8. Coherent Clock Generator
IN
ADF4001
ADF4001
f
R1
f
OUT
S
= (f
IN
=
IN
REF
N1)/(R1
comes from the signal generator, the
N1
N2
IN
×
N2)
RF
RF
MUXOUT
CP
(
N
IN
IN
RF
S
, the sampling clock.
÷
FILTER
LOOP
R
f
IN
)
NC7S04
A
100MHz
IN
SAMPLING
VCO
CLOCK
CONVERTER
f
S
UNDER
TEST
OUT
A/D
IN
–14–
FREF
MASTER
CLOCK
52MHz
IN
7
CPGND
AV
V
Figure 10. Local Oscillator Shutdown Circuit
Figure 9. Tri-Band System Clock Generation
DD
DD
REF
REF
REF
3
ADF4001
15
DV
IN
IN
IN
DD
AGND
16
4
V
V
ADF4001
ADF4001
R2
1300
ADF4001
P
486
P
N2
POWER-DOWN CONTROL
24
65
R3
N3
R1
4
1
N1
DGND
RF
RF
CE
R
SET
IN
10
CP
IN
9
A
B
6
5
1
2
100pF
DECOUPLING CAPACITORS AND INTERFACE
SIGNALS HAVE BEEN OMITTED FROM THE
DIAGRAM IN THE INTEREST OF GREATER CLARITY.
FILTER
100pF
10k
LOOP
CP
RF
CP
RF
CP
RF
IN
IN
IN
RF
RF
RF
FILTER
FILTER
FILTER
LOOP
LOOP
LOOP
IN
51
ADG702
V
GND
CC
S
D
VCXO
VCO
OR
19.44MHz
19.2MHz
GND
13MHz
V
VCXO
VCXO
VCXO
DD
100pF
CLOCK FOR WCDMA
CLOCK FOR CDMA
19.44MHz SYSTEM
CLOCK FOR GSM
19.2MHz SYSTEM
13MHz SYSTEM
100pF
18
REV. A
18
18
RF
OUT