ADF4360-7BCPZ Analog Devices Inc, ADF4360-7BCPZ Datasheet
ADF4360-7BCPZ
Specifications of ADF4360-7BCPZ
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ADF4360-7BCPZ Summary of contents
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... Integrated Synthesizer and VCO GENERAL DESCRIPTION The ADF4360 integrated integer-N synthesizer and voltage controlled oscillator (VCO). The ADF4360-7 center frequency is set by external inductors. This allows a frequency range of between 350 MHz to 1800 MHz. In addition, a divide- by-2 option is available, whereby the user receives an RF output of between 175 MHz and 900 MHz ...
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... ADF4360-7 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 Transistor Count........................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Circuit Description......................................................................... 10 Reference Input Section............................................................. 10 Prescaler (P/P + 1)...................................................................... 10 A and B Counters ....................................................................... 10 R Counter .................................................................................... 10 PFD and Charge Pump.............................................................. 10 MUXOUT and Lock Detect...................................................... 11 Input Shift Register ...
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... DV – 0.4 V min CMOS output chosen. DD 500 µA max 0.4 V max I = 500 µA. OL 3.0/3.6 V min/V max typ 2.5 mA typ 14.0 mA typ mA. CORE 3.5 to 11.0 mA typ RF output stage is programmable. 7 µA typ Rev Page 4.7 kΩ. SET ≤ 2 ≤ 2 ADF4360-7 ...
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... REFIN PFD MHz MHz 500; loop B kHz. REFIN PFD 13 The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REF for the synthesizer MHz @ 0 dBm. REFOUT B Version Unit Conditions/Comments 1800 MHz ...
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... DB22 DB2 (CONTROL BIT C2) Figure 2. Timing Diagram Rev Page ADF4360 unless otherwise noted. A MIN MAX Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width ...
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... ADF4360-7 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND GND VCO VCO DD Digital I/O Voltage to GND Analog I/O Voltage to GND REF to GND IN Operating Temperature Range Maximum Junction Temperature CSP θ Thermal Impedance JA Paddle Soldered Paddle Not Soldered Lead Temperature, Soldering ...
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... TUNE voltage external inductor to AGND should be connected to this pin to set the ADF4360-7 output frequency. L1 and L2 need to be the same value. For inductances greater than 3.3 nH, a 470 Ω resistor should be added in parallel to AGND external inductor to AGND should be connected to this pin to set the ADF4360-7 output frequency. L1 and L2 need to be the same value. For inductances greater than 3.3 nH, a 470 Ω ...
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... ADF4360-7 TYPICAL PERFORMANCE CHARACTERISTICS –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 100 1k 10k 100k FREQUENCY OFFSET (Hz) Figure 4. Open-Loop VCO Phase Noise, L1 –70 –75 –80 –85 –90 –95 –100 –105 –110 –115 –120 –125 –130 –135 –140 – ...
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... MHz Channel Spacing, 25 kHz Loop Bandwidth) Rev Page ADF4360 3.3V 3.3V DD VCO REFERENCE I = 2.5mA CP LEVEL = –3.5dBm PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 10kHz RES. BANDWIDTH = 30Hz VIDEO BANDWIDTH = 30Hz SWEEP = 1.9 SECONDS AVERAGES = 20 – ...
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... ADF4360-7 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 16. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures that there is no loading of the REF on power-down ...
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... VCO The VCO core in the ADF4360 family uses eight overlapping bands, as shown in Figure 20, to allow a wide frequency range to be covered without a large VCO sensitivity (K poor phase noise and spurious performance. The correct band is chosen automatically by the band select logic at power-up or whenever the N counter latch is updated important that the correct write sequence be followed at power-up ...
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... K is determined by the value of inductors used V (see the Choosing the Correct Inductance section). If divide-by- 2 operation has been selected (by programming DIV2 [DB22] high in the N counter latch), the value is halved. The ADF4360 family contains linearization circuitry to minimize any variation of the product of I and K . ...
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... LATCH STRUCTURE Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs decide which latch is programmed. Table 6. Latch Structure PRESCALER CURRENT VALUE SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 ...
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... ADF4360-7 Table 7. Control Latch PRESCALER CURRENT VALUE SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 PD1 CPI6 CPI5 CPI4 CPI6 CPI5 CPI3 CPI2 PL2 PIN PD2 PD1 PRESCALER VALUE 16/ 32/33 ...
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... PRESCALER VALUE SET IN THE CONTROL LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF (N × THE OUTPUT, N REF ADF4360-7 CONTROL BITS DB2 DB1 DB0 A1 C2 (1) C1 (0) A COUNTER DIVIDE RATIO –P). MIN ...
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... ADF4360-7 Table 9. R Counter Latch BAND BACKLASH SELECT CLOCK DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 RSV RSV BSC2 BSC1 TMB LDP ABP2 TEST MODE BIT SHOULD BE SET TO 0 FOR NORMAL THESE BITS ARE NOT OPERATION ...
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... VCO may not oscillate at the desired frequency, which does not allow the band select logic to choose the correct frequency band, and the ADF4360-7 may not achieve lock. If the recom- mended interval is inserted, and the N counter latch is pro- grammed, the band select logic can choose the correct fre- quency band, and the part locks to the correct frequency ...
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... ADF4360-7 Hardware Power-Up/Power-Down If the part is powered down via the hardware (using the CE pin) and powered up again without any change to the N counter register during power-down, the part locks at the correct fre- quency, because the part is already in the correct frequency band. The lock time depends on the value of capacitance on the C pin, which is < ...
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... With (C2, C1) = (0,0), the control latch is programmed. Table 7 shows the input data format for programming the control latch. Prescaler Value In the ADF4360 family, P2 and P1 in the control latch set the prescaler values. Power-Down DB21 (PD2) and DB20 (PD1) provide programmable power- down modes ...
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... The overall divide range is defined by ((P × A), where P is the prescaler value. CP Gain DB21 of the N counter latch in the ADF4360 family is the charge pump gain bit. When this is programmed to 1, Current Setting 2 is used. When programmed to 0, Current Setting 1 is used. This bit can also be programmed through DB10 of the control latch ...
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... This allows frequencies as low as 8 MHz and as high as 137 MHz to be generated using a single system. In the circuit drawn in Figure 23, the ADF4360-7 is being used to generate 1024 MHz, and the ADF4007 is being used to divide provide a channel spacing of 100 kHz, a PFD frequency of 800 kHz is used for the ADF4360-7 PLL. The loop bandwidth is chosen kHz ...
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... FIXED FREQUENCY LO Figure 26 shows the ADF4360-7 used as a fixed frequency LO at 500 MHz. The low-pass filter was designed using ADIsimPLL for a channel spacing of 8 MHz and an open-loop bandwidth of 30 kHz ...
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... The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4360 family needs a 24-bit word, which is accomplished by writing three 8-bit bytes from the MicroConverter to the device. After the third byte has been written, the LE input should be brought high to complete the transfer ...
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... Experiments have shown that the circuit shown in Figure 30 provides an excellent match to 50 Ω over a limited operating range of the ADF4360-7 (850 MHz to 950 MHz). This gives approximately −2 dBm output power across the specific frequency range of the ADF4360-7 using 3.9 nH. For other frequencies, a tuned LC is recommended ...
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... ADF4360-7BCPRL −40°C to +85°C ADF4360-7BCPRL7 −40°C to +85°C 1 ADF4360-7BCPZ −40°C to +85°C 1 ADF4360-7BCPZRL −40°C to +85°C 1 ADF4360-7BCPZRL7 −40°C to +85°C EVAL-ADF4360-7EB1 Pb-free part. 4.00 BSC SQ 0.60 MAX 0.50 BSC TOP 3.75 VIEW BSC SQ 0 ...
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... ADF4360-7 NOTES Rev Page ...
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... NOTES Rev Page ADF4360-7 ...
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... ADF4360-7 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective owners. D04441– ...