ADF4360-7BCPZ Analog Devices Inc, ADF4360-7BCPZ Datasheet - Page 7

• Manufacturer Part Number: ADF4360-7BCPZ
• Description: IC SYNTHESIZER/VCO 24-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Distribution, Integer N Synthesizer (RF)r

Specifications of ADF4360-7BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 1.8GHz
• Pll Type: Frequency Synthesis
• Frequency: 1.8GHz
• Supply Current: 10mA
• Supply Voltage Range: 3V To 3.6V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 24
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4360-7EBZ1 - BOARD EVALUATION FOR ADF4360-7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3, 8, 11, 22
4
5
6
7
9
10
12
13
14
15
16
17
18
19
20
21
23
24
L2
CLK
DATA
LE
Mnemonic
CPGND
AV
AGND
RF
RF
V
V
L1
C
R
C
DGND
REF
MUXOUT
DV
CE
CP
SET
VCO
TUNE
C
N
OUT
OUT
DD
DD
IN
A
B
Function
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be
placed as close as possible to this pin. AV
Analog Ground. This is the ground return path of the prescaler and VCO.
VCO Output. The output level is programmable from −5 dBm to −14 dBm. See the Output Matching section for a
description of the various output stages.
VCO Complementary Output. The output level is programmable from −5 dBm to −14 dBm. See the Output Matching
section for a description of the various output stages.
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should
be placed as close as possible to this pin. V
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output
voltage.
An external inductor to AGND should be connected to this pin to set the ADF4360-7 output frequency. L1 and L2
need to be the same value. For inductances greater than 3.3 nH, a 470 Ω resistor should be added in parallel to AGND.
An external inductor to AGND should be connected to this pin to set the ADF4360-7 output frequency. L1 and L2
need to be the same value. For inductances greater than 3.3 nH, a 470 Ω resistor should be added in parallel to AGND.
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the
synthesizer. The nominal voltage potential at the R
where R
Internal Compensation Node. This pin must be decoupled to V
Digital Ground.
Reference Input. This is a CMOS input with a nominal threshold of V
100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit
shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, and the relevant latch is selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed
externally.
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DV
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
Taking the pin high powers up the device depending on the status of the power-down bits.
Charge Pump Output. When enabled, this provides ± I
I
CPmax
SET
= 4.7 kΩ, and I
=
11.75
R
SET
RF
RF
CPGND
AGND
AV
OUT
OUT
V
CPmax
VCO
DD
A
B
= 2.5 mA.
1
2
3
4
5
6
Figure 3. Pin Configuration
Rev. A | Page 7 of 28
ADF4360-7
PIN 1
IDENTIFIER
(Not to Scale)
TOP VIEW
DD
DD
VCO
must have the same value as DV
must have the same value as AV
must have the same value as AV
SET
CP
to the external loop filter, which in turn drives the internal VCO.
pin is 0.6 V. The relationship betwe
18
17
16
15
14
13
DATA
CLK
REF
DGND
C
R
N
SET
VCO
IN
with a 10 µF capacitor.
DD
/2 and a dc equivalent input resistance of
DD
DD
.
.
DD
.
en
I
CP
and R
ADF4360-7
SET
is