SI4114G-BM Silicon Laboratories Inc, SI4114G-BM Datasheet - Page 15

• Manufacturer Part Number: SI4114G-BM
• Description: GSM FREQ SYNTH FOR DIRECT CONV
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4114G-BM

• Package / Case: 28-QFN
• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 1.99GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 2.9 V
• Operating Temperature: -20°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 1.99GHz
• Operating Frequency: 1710 to 1990 MHz
• Supply Current: 18 mA
• Operating Temperature Range: - 20 C to + 70 C
• Mounting Style: SMD/SMT
• Power Gain Typ: 2.4 dB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

automatically selects the corresponding multiplexed
output.
The reference frequency on the XIN pin is divided by R
and this signal is the input to the PLL’s phase detector.
The other input to the phase detector is the PLL’s VCO
output frequency divided by N. The PLL works to make
these frequencies equal after an initial transient:
or
For XIN = 13 MHz or for XIN = 26 MHz and R = 65 or
R = 130 respectively, this simplifies to the following:
The integer N is set by programming the RF1 N-Divider
register (Register 3) and the RF2 N-Divider register
(Register 4).
Each N divider consists of a dual-modulus prescaler, a
swallow counter, and a lower speed synchronous
counter. However, the calculation of these values is
done automatically. Only the appropriate N value needs
to be programmed.
The PLL R-divider option (Register 0, RDIV bit) can be
programmed to either R = 65 or R = 130 to yield a
200 kHz phase detector update rate with either a
13 MHz or 26 MHz reference frequency, respectively.
3.4. PLL Loop Dynamics
The transient response for each PLL has been
optimized for a GSM application. VCO gain, phase
detector gain, and loop filter characteristics are not
programmable.
The settling time for each PLL is directly proportional to
its phase detector update period Tφ (Tφ equals 1/fφ). For
a GSM application with a 200 kHz phase detector
update rate, the PLL is Tφ = 5 µS. During the first 6.5
update periods, the Si4114G executes the self-tuning
algorithm. Thereafter the PLL controls the output
frequency. Because of the unique architecture of the
Si4114G PLLs, the time required to settle the output
frequency to 0.1 ppm error is approximately 21 update
periods. Thus, the total time after powerup or a change
in
frequency is well settled (including time for self-tuning)
is around 28 update periods or 140 µS.
3.5. RF Outputs (RFOUT)
The RFOUT pin is driven by an amplifier that buffers the
output pin from the RF VCOs, and must be coupled to
programmed
f
OUT
frequency
f
OUT
f
----------- -
OUT
N
=
=
N 200
=
N
--- -
R
×
f
-----------
×
REF
R
f
until
REF
kHz
the
synthesized
Rev. 1.1
its load through an ac coupling capacitor. The amplifier
is driven by either the RF1 or RF2 VCO, depending
upon which N-Divider register was last written to. For
example, programming the N-Divider register for RF1
automatically selects the RF1 VCO output.
A matching network is recommended to maximize
power delivered into a 50 Ω load. The network typically
consists of a less than 2 nH series inductance, which
may be realized with a PC board trace, connected
between the RFOUT pin and the ac coupling capacitor.
The network is made to provide an adequate match for
both the RF1 and RF2 frequency bands, and also filters
the output signal to reduce harmonic distortion. A 50 Ω
load is not required for proper operation of the Si4114G.
Depending on transceiver requirements, the matching
network might not be needed. See Figure 11.
3.6. Reference Frequency Amplifier
The Si4114G provides a reference frequency amplifier.
If the driving signal has CMOS levels it can be
connected directly to the XIN pin. Otherwise, the
reference frequency signal should be ac coupled to the
XIN pin through a 560 pF capacitor.
3.7. Powerdown Modes
Table 6 summarizes the powerdown functionality. The
Si4114G can be powered down by taking the PWDN pin
low or by setting bits in the Powerdown register
(Register 1). When the PWDN pin is low, the Si4114G
will be powered down regardless of the Powerdown
register settings. When the PWDN pin is high, power
management is under control of the Powerdown register
bits.
3.8. Auxiliary Output (AUXOUT)
The signal appearing on AUXOUT is selected by setting
the AUXSEL bits in the Main Configuration register
(Register 0).
A lock detect (LDETB) signal can be selected by setting
the AUXSEL bits to 11. As discussed previously, this
signal can be used to indicate that the PLL is about to lose
lock due to excessive ambient temperature drift and
should be re-tuned.
RFOUT
Figure 11. RFOUT 50 Ω Test Circuit
<2 nH
560 pF
Si4114G
50
Ω
15