AD9517-4BCPZ Analog Devices Inc, AD9517-4BCPZ Datasheet - Page 57

• Manufacturer Part Number: AD9517-4BCPZ
• Description: IC CLOCK GEN 1.8GHZ VCO 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9517-4BCPZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:12
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.8GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 1.8GHz
• No. Of Outputs: 12
• Supply Current: 100µA
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Rohs Compliant: Yes
• For Use With: AD9517-4/PCBZ - BOARD EVALUATION AD9517-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr.
(Hex)
LVPECL Channel Dividers
0x190
0x191
0x192
0x193
to
0x195
0x196
0x197
0x198
LVDS/CMOS Channel Dividers
0x199
0x19A
0x19B
0x19C
0x19D
0x19E
0x19F
0x1A0
0x1A1
0x1A2
0x1A3
0x1A4
to
0x1DF
VCO Divider and CLK Input
0x1E0
0x1E1
0x1E2
to
0x22A
System
0x230
0x231
Update All Registers
0x232
Parameter
Divider 0
(PECL)
Divider1
(PECL)
Divider 2
(LVDS/CMOS)
Divider 3
(LVDS/CMOS)
VCO divider
Input CLKs
and SYNC
Update all
registers
Power-down
Bit 7 (MSB)
Divider 0
bypass
Blank
Divider 1
bypass
Reserved
Reserved
Blank
Blank
Blank
Bit 6
Divider 0
nosync
Divider 1
nosync
Reserved
Phase Offset Divider 2.2
Phase Offset Divider 3.2
Low Cycles Divider 2.1
Low Cycles Divider 2.2
Low Cycles Divider 3.1
Low Cycles Divider 3.2
Divider 0 low cycles
Divider 1 low cycles
Blank
Blank
Bit 5
Divider 0
force high
Divider 1
force high
Bypass
Divider 2.2
Bypass
Divider 3.2
Reserved
Rev. B | Page 57 of 80
Bit 4
Divider 0
start high
Divider 1
start high
Bypass
Divider 2.1
Bypass
Divider 3.1
Power-
down
clock input
section
Blank
Reserved
Reserved
Reserved
Reserved
Blank
Blank
Bit 3
Divider 2
nosync
Divider 3
nosync
Reserved
Power-down
VCO clock
interface
Reserved
Reserved
Bit 2
Divider 2
force high
Divider 3
force high
Power-
down VCO
and CLK
Power-
down SYNC
Phase Offset Divider 2.1
Phase Offset Divider 3.1
High Cycles Divider 2.1
High Cycles Divider 2.2
High Cycles Divider 3.1
High Cycles Divider 3.2
Divider 0 phase offset
Divider 1 phase offset
Divider 0 high cycles
Divider 1 high cycles
Reserved
Bit 1
Divider 0
direct to
output
Divider 1
direct to
output
Start High
Divider 2.2
Start High
Divider 3.2
Select
VCO or CLK
Power-
down
distribution
reference
VCO Divider
Bit 0 (LSB)
Divider 0
DCCOFF
Divider 1
DCCOFF
Start High
Divider 2.1
Divider 2
DCCOFF
Start High
Divider 3.1
Divider 3
DCCOFF
Bypass VCO
divider
Soft SYNC
Update all
registers (self-
clearing bit)
AD9517-4
0x00
0x80
0x00
0x00
0x22
0x00
0x11
0x22
0x00
0x11
0x00
0x00
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
0x00