LMX2325TM National Semiconductor, LMX2325TM Datasheet - Page 20

• Manufacturer Part Number: LMX2325TM
• Description: IC FREQ SYNTHESIZER 20-TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2325TM

• Pll: Yes
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/No
• Frequency - Max: 2.5GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 2.5GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LMX2325TM

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Application Information
The phase noise level at 150 Hz offset is −81.1 dBc/Hz. The
spurs at 60 and 180 Hz offset are due to 60 Hz line noise
from the power supply.
The phase noise level at 20 kHz offset is −80 dBc/Hz.
FIGURE 11. PLL Phase Noise
FIGURE 12. PLL Phase Noise 20 kHz Offset
@
150 Hz Offset
(Continued)
DS012339-36
DS012339-35
20
Of concern in any PLL loop filter design is the time it takes to
lock in to a new frequency when switching channels. Figure
13 shows the switching waveforms for a frequency jump of
1650.9 MHz to 1683.9 MHz. By narrowing the frequency
span of the HP53310A Modulation Domain Analyzer enables
evaluation of the frequency lock time to within
lock time is seen to be less than 500 µs for a frequency jump
of 33 MHz.
EXTERNAL CHARGE PUMP
The LMX PLLatinum series of frequency synthesizers are
equipped with an internal balanced charge pump as well as
outputs for driving an external charge pump. Although the
superior performance of NSC’s on board charge pump elimi-
nates the need for an external charge pump in most appli-
cations, certain system requirements are more stringent. In
these cases, using an external charge pump allows the
designer to take direct control of such parameters as charge
pump voltage swing, current magnitude, TRI-STATE leak-
age, and temperature compensation.
One possible architecture for an external charge pump cur-
rent source is shown in Figure 14 . The signals
the diagram, correspond to the phase detector outputs of the
2315/20/25 frequency synthesizers. These logic signals are
converted into current pulses, using the circuitry shown in
Figure 14 , to enable either charging or discharging of the
loop filter components to control the output frequency of the
PLL.
Referring to Figure 14 , the design goal is to generate a 5 mA
current which is relatively constant to within 5V of the power
supply rail. To accomplish this, it is important to establish as
large of a voltage drop across R5, R8 as possible without
saturating Q2, Q4. A voltage of approximately 300 mV pro-
vides a good compromise. This allows the current source
reference being generated to be relatively repeatable in the
absence of good Q1, Q2/Q3, Q4 matching. (Matched tran-
sistor pairs is recommended.) The p and r outputs are
rated for a maximum output load current of 1 mA while 5 mA
current sources are desired. The voltages developed across
R4, 9 will consequently be approximately 258 mV, or 42 mV
less than R8, 5, due to the current density differences
{0.026
In order to calculate the value of R7 it is necessary to first
estimate the forward base to emitter voltage drop (Vfn,p) of
*
1n (5 mA/1 mA)} through the Q1, Q2/Q3, Q4 pairs.
FIGURE 13. Frequency Jump Lock Time
±
1 kHz. The
p
DS012339-37
and
r
in