MPC973FA Freescale Semiconductor, MPC973FA Datasheet

MPC973FA

Manufacturer Part Number

MPC973FA

Description

IC PLL CLOCK DRIVER 52-LQFP

Manufacturer

Freescale Semiconductor

Type

Clock Driver, Fanout Distribution, Multiplexerr

Datasheet

1.MPC973FA.pdf (16 pages)

Specifications of MPC973FA

Pll

Yes with Bypass

Input

LVCMOS, LVTTL

Output

LVCMOS

Number Of Circuits

Ratio - Input:output

4:12

Differential - Input:output

No/No

Frequency - Max

125MHz

Divider/multiplier

Yes/Yes

Voltage - Supply

3.135 V ~ 3.465 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

52-LQFP

Frequency-max

125MHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

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Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

MPC973FA

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MOT

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Part Number:

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MPC973FAR2

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20 000

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Low Voltage PLL Clock Driver

targeted for high performance CISC or RISC processor based systems.

With output frequencies of up to 125 MHz and skews of 550 ps the MPC973

is ideally suited for most synchronous systems. The device offer twelve low

skew outputs plus a feedback and sync output for added flexibility and ease

of system implementation.

• Fully Integrated PLL

• Output Frequency up to 125 MHz

• Compatible with PowerPC and Pentium Microprocessors

• LQFP Packaging

• 3.3 V V

• ± 100ps Typical Cycle–to–Cycle Jitter

between the 12 outputs as well as the input vs output relationships. Using

the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2,

5:3, 6:1 and 6:5 between outputs can be realized by pulsing low one clock

edge prior to the coincident edges of the Qa and Qc outputs. The Sync

output will indicate when the coincident rising edges of the above

relationships will occur. The selectability of the feedback frequency is

independent of the output frequencies, this allows for very flexible

programming of the input reference vs output frequency relationship. The

output frequencies can be either odd or even multiples of the input

reference. In addition the output frequency can be less than the input

frequency for applications where a frequency needs to be reduced by a

non–binary factor. The Power–On Reset ensures proper programming if the

frequency select pins are set at power up. If the fselFB2 pin is held high, it

m a y b e n e c e s s a r y t o a p p l y a r e s e t a f t e r p o w e r – u p t o e n s u r e

synchronization between the QFB output and the other outputs. The internal

power–on reset is designed to provide this function, but with power–up

conditions being dependent, it is difficult to guarantee. All other conditions of

the fsel pins will automatically synchronize during PLL lock acquisition.

well as provide unique opportunities for system power down schemes to meet the requirements of “green” class machines. The

MPC973 allows for the enabling of each output independently via a serial input port. When disabled or “frozen” the outputs will be

locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “unfrozen” the outputs will

activate synchronous and in phase with those outputs which were not frozen. The freezing and unfreezing of outputs occurs only

when they are already in the “LOW” state, thus the possibility of runt pulse generation is eliminated. A power-on reset will ensure

that upon power up all of the outputs will be active. Note that all of the control inputs on the MPC973 have internal pull–up resistors.

compatible levels while the outputs provide LVCMOS levels with the capability to drive 50 Ω transmission lines. For series

terminated lines each MPC973 output can drive two 50 Ω lines in parallel thus effectively doubling the fanout of the device.

AN1545/D in the Advanced Clock Drivers Device Data book (DL207/D) for a discussion on the thermal issues with the MPC family

of clock drivers.

PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA



The MPC973 is a 3.3 V compatible, PLL based clock driver device

The MPC973 features an extensive level of frequency programmability

The MPC973 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system debug as

The MPC973 is fully 3.3 V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL

The MPC973 can consume significant power in some configurations. Users are encouraged to review Application Note

Motorola, Inc. 2001

PLL CLOCK DRIVER

52–LEAD LQFP PACKAGE

LOW VOLTAGE

MPC973

CASE 848D-03

FA SUFFIX

SCALE 2:1

Order Number: MPC973/D

Rev. 2, 09/2001

Related parts for MPC973FA

MPC973FA Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC973 is a 3.3 V compatible, PLL based clock driver device targeted for high performance CISC or RISC processor based systems. With output frequencies 125 MHz and ...

Page 2

MPC973 FUNCTION TABLE 1 fsela1 fsela0 Qa ÷ ÷ ÷ ÷ FUNCTION TABLE 2 *fselFB2 fselFB1 fselFB0 ...

Page 3

MOTOROLA ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ Figure 2. Logic Diagram MPC973 3 ...

Page 4

MPC973 ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ 4 1:1 Mode 2:1 Mode 3:1 Mode 3:2 Mode 4:1 Mode 4:3 Mode 6:1 Mode Figure 3. Timing Diagrams MOTOROLA ...

Page 5

ABSOLUTE MAXIMUM RATINGS* Symbol V Supply Voltage CC V Input Voltage I I Input Current IN T Storage Temperature Range Stor * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these ...

Page 6

MPC973 AC CHARACTERISTICS (T = 0° to 70° Symbol Characteristic Output Rise/Fall Time Output Duty Cycle pw t SYNC to Feedback pd Propagation Delay t Output-to-Output Skew os f VCO Lock Range ...

Page 7

Using the MPC973 as a Zero Delay Buffer The external feedback of the MPC973 clock driver allows for its use as a zero delay buffer. By using one of the outputs as a feedback to the PLL the propagation delay ...

Page 8

MPC973 Figure 5. Typical Static Phase Offset versus Reference Frequency T versus TCLK pd Figure 7. Typical Phase Jitter versus Reference Frequency 8 Figure 4. Typical Skews Relative to QFB Figure 6. Typical Static Phase Offset versus Reference Frequency I/O ...

Page 9

MPC973 Figure 8. Programming Configuration Example Figure 10. Generating MPC604 Clocks from Ethernet Clocks MPC973 Figure 11. Phase Delay Using Multiple MPC973’s Recommended External Reset Timing For MPC973 applications requiring synchronization of the output clock to the input clock and ...

Page 10

MPC973 Figure 12. Assertion of MR Power Supply Filtering The MPC973 is a mixed analog/digital product and exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially ...

Page 11

MPC973. The output waveform in Figure 15 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the ...

Page 12

MPC973 VIEW Y 3X –L– –N– –H– –T– SEATING 4X PLANE C2 C1 VIEW AA 12 OUTLINE DIMENSIONS FA SUFFIX LQFP PACKAGE CASE 848D–03 ISSUE TIPS ...

Page 13

MOTOROLA NOTES MPC973 13 ...

Page 14

MPC973 14 NOTES MOTOROLA ...

Page 15

MOTOROLA NOTES MPC973 15 ...

Page 16

MPC973 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out ...

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