MPC973FA Freescale Semiconductor, MPC973FA Datasheet - Page 10

• Manufacturer Part Number: MPC973FA
• Description: IC PLL CLOCK DRIVER 52-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Driver, Fanout Distribution, Multiplexerr

Specifications of MPC973FA

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 4:12
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Power Supply Filtering
some sensitivities that would not necessarily be seen on a fully
digital product. Analog circuitry is naturally susceptible to
random noise, especially if this noise is seen on the power
supply pins. The MPC973 provides separate power supplies for
the output buffers (V
device. The purpose of this design technique is to try and isolate
the high switching noise digital outputs from the relatively
sensitive internal analog phase–locked loop. In a controlled
environment such as an evaluation board this level of isolation
is sufficient. However, in a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simplest form of
isolation is a power supply filter on the V
MPC973.
MPC973 is most susceptible to noise with spectral content in
the 1 KHz to 1 MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs to
be met in the final filter design is the DC voltage drop that will
be seen between the V
MPC973. From the data sheet the I
sourced through the V
maximum), assuming that a minimum of 2.935 V must be
maintained on the V
tolerated when a 3.3 V V
in Figure 13 must have a resistance of 5–10 Ω to meet the
voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for noise
whose spectral content is above 20 KHz. As the noise
MPC973
The MPC973 is a mixed analog/digital product and exhibits
Figure 13 illustrates a typical power supply filter scheme. The
10
Figure 13. Power Supply Filter
Figure 12. Assertion of MR
CCA
CCO
CCA
CC
pin very little DC voltage drop can be
CC
) and the internal PLL (V
supply is used. The resistor shown
supply and the V
pin) is typically 15 mA (20 mA
µ
VCCA
µ
Ω
current (the current
µ
CCA
CCA
CCA
pin for the
pin of the
) of the
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the bandwidth
of the PLL.
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may be
applications in which overall performance is being degraded
due to system power supply noise. The power supply filter
schemes discussed in this section should be adequate to
eliminate power supply noise related problems in most designs.
Driving Transmission Lines
signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of approximately 10 Ω the drivers can
drive either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
application note AN1091 in the Timing Solutions data book
(DL207/D).
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to V
level of DC current and thus only a single terminated line can
be driven by each output of the MPC973 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 14 illustrates an output driving a single series terminated
line vs two series terminated lines in parallel. When taken to its
extreme the fanout of the MPC973 clock driver is effectively
doubled due to its capability to drive multiple lines.
of an output driving a single line vs two lines. In both cases the
drive capability of the MPC973 output buffers is more than
sufficient to drive 50 Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43 ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used
Although the MPC973 has several design features to
The MPC973 clock driver was designed to drive high speed
In most high performance clock networks point–to–point
The waveform plots of Figure 15 show the simulation results
Figure 14. Single versus Dual Transmission Lines
Ω
Ω
CC
/2. This technique draws a fairly high
Ω
Ω
Ω
Ω
Ω
Ω
MOTOROLA