LMX2335USLBX National Semiconductor, LMX2335USLBX Datasheet - Page 29

• Manufacturer Part Number: LMX2335USLBX
• Description: IC FREQ SYNTH DUAL 16LAMINATECSP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2335USLBX

• Pll: Yes with Bypass
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: No/No
• Frequency - Max: 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-Laminate CSP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2335USLBXTR

Test Setups
The block diagram above illustrates the setup required to
measure the LMX2336U device’s RF1 input sensitivity level.
The same setup is used for the LMX2336TMEB/
LMX2336SLEEB Evaluation Boards. The RF2 input sensitiv-
ity test setup is similar to the RF1 sensitivity test setup. The
purpose of this test is to measure the acceptable signal level
to the f
signal range, the feedback divider begins to divide incor-
rectly and miscount the frequency.
The setup uses an open loop configuration. A power supply
is connected to V
to 5.5V. The RF2 PLL is powered down (PWDN RF2 Bit = 1).
By means of a signal generator, an RF signal is applied to
the f
between the PLL and the signal generator. The OSC
tied to V
Loader, i.e. RF1 N_CNTRB Word = 156 and RF1 N_CNTRA
Word = 16 for PRE RF1 Bit = 0. The feedback divider output
is routed to the F
Output word (F
Universal Counter is connected to the F
IN
IN
RF1 pin. The 3 dB pad provides a 50 Ω match
cc
RF1 input of the PLL chip. Outside the acceptable
. The N value is typically set to 10000 in Code
o
o
cc
LD pin by selecting the RF1 PLL N Divider
LD Word = 6 or 14) in Code Loader. A
and the bias voltage is swept from 2.7V
(Continued)
LMX2335U and LMX2336U f
o
LD pin and tied to
in
pin is
29
IN
the 10 MHz reference output of the signal generator. The
output of the feedback divider is thus monitored and should
be equal to f
The f
with the signal generator. The measurements are repeated
at different temperatures, namely T
+85˚C. Sensitivity is reached when the frequency error of the
divided RF input is greater than or equal to 1 Hz. The power
attenuation from the cable and the 3 dB pad must be ac-
counted for. The feedback divider will actually miscount if too
much or too little power is applied to the f
Therefore, the allowed input power level will be bounded by
the upper and lower sensitivity limits. In a typical application,
if the power level to the f
sitivity limits, this can introduce spurs and degradation in
phase noise. When the power level gets even closer to these
limits, or exceeds it, then the RF1 PLL loses lock.
The LMX2335U f
to the above test setup.
Sensitivity Test Setup
IN
RF1 input frequency and power level are then swept
IN
RF1 / N.
IN
sensitivity test setup is very much similar
IN
RF1 input approaches the sen-
A
= -40˚C, +25˚C, and
IN
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RF1 input.
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