LMX2377UTM National Semiconductor, LMX2377UTM Datasheet - Page 33

• Manufacturer Part Number: LMX2377UTM
• Description: IC FREQ SYNTH DUAL 20TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2377UTM

• Pll: Yes with Bypass
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 2.5GHz, 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 2.5GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LMX2377UTM

1.0 Functional Description
1.8.2 Open Drain FastLock Output
The LMX233xU Fastlock feature allows faster loop response
time during lock aquisition. The loop response time (lock
time) can be approximately halved if the loop bandwidth is
doubled. In order to achieve this, the same gain/ phase
relationship at twice the loop bandwidth must be maintained.
This can be achieved by increasing the charge pump current
from 0.95 mA (ID
3.8 mA (ID
is configured as a FastLock output, an open drain device is
enabled. The open drain device switches in a parallel resis-
tor R2’ to ground, of equal value to resistor R2 of the external
loop filter. The loop bandwidth is effectively doubled and
stability is maintained. Once locked to the correct frequency,
the PLL will return to a steady state condition. Refer to
Section 2.8 F
output to an open drain Fastlock output.
1.8.3 Counter Reset
Three separate counter reset functions are provided. When
the F
the Aux feedback divider and the Aux reference divider are
held at their load point. When the Reset Main PLL
Counters is programmed, both the Main feedback divider
and the Main reference divider are held at their load point.
When the Reset All Counters mode is enabled, all feedback
dividers and reference dividers are held at their load point.
When the device is programmed to normal operation, both
the feedback divider and reference divider are enabled and
resume counting in ‘close’ alignment to each other. Refer to
Section 2.8 F
1.8.4 Reference Divider and Feedback Divider Output
The outputs of the various N and R divders can be monitored
by selecting the appropriate F
when performing OSC
fer to the Test Setups section for more details. Refer to
Section 2.8 F
divder output to the F
Notes:
1. TRI-STATE ID
2. PWDN refers to either the PWDN Main or PWDN Aux bit.
TRI-STATE ID
o
LD is programmed to Reset Aux PLL Counters, both
o
0
1
0
1
Main Bit = 1) in Fastlock. When the F
o
o
o
LD for details on how to route the appropriate
LD for more details.
LD for details on how to configure the F
o
o
o
Main Bit = 0) in the steady state mode, to
refers to either the TRI-STATE ID
o
in
LD pin.
or f
IN
sensitivity measurements. Re-
o
LD word. This is essential
PWDN
0
0
1
1
(Continued)
o
LD output
o
Main or TRI-STATE ID
o
LD
PLL Active, Normal Operation
PLL Active, Charge Pump Output in High Impedance State
Synchronous Powerdown
Asynchronous Powerdown
33
1.9 POWER CONTROL
Each synthesizer in the LMX2377U device is individually
power controlled by device powerdown bits. The powerdown
word is comprised of the PWDN Main (PWDN Aux) bit, in
conjuction with the TRI-STATE ID
Aux) bit. The powerdown control word is used to set the
operating mode of the device. Refer to Sections 2.4.4,
2.5.4, 2.6.4, and 2.7.4 for details on how to program the Main
or Aux powerdown bits.
When either the Main synthesizer or the Aux synthesizer
enters the powerdown mode, the respective prescaler,
phase detector, and charge pump circuit are disabled. The
D
forced to a high impedance state. The reference divider and
feedback divider circuits are held at the load point during
powerdown. The oscillator buffer is disabled when both the
Main and Aux synthesizers are powered down. The OSC
pin is forced to a HIGH state through an approximate 100 kΩ
resistance when this condition exists. When either synthe-
sizer is activated, the respective prescaler, phase detector,
charge pump circuit, and the oscillator buffer are all powered
up. The feedback divider, and the reference divider are held
at load point. This allows the reference oscillator, feedback
divider, reference divider and prescaler circuitry to reach
proper bias levels. After a finite delay, the feedback and
reference dividers are enabled and they resume counting in
‘close’ alignment (the maximum error is one prescaler cycle).
The MICROWIRE control register remains active and ca-
pable of loading and latching data while in the powerdown
mode.
Synchronous Powerdown Mode
In this mode, the powerdown function is gated by the charge
pump. When the device is configured for synchronous pow-
erdown, the device will enter the powerdown mode upon
completion of the next charge pump pulse event.
Asynchronous Powerdown Mode
In this mode, the powerdown function is NOT gated by the
completion of a charge pump pulse event. When the device
is configured for asynchronous powerdown, the part will go
into powerdown mode immediately.
o
Main (D
o
Aux bit .
o
Aux), f
Operating Mode
IN
Main (f
IN
Aux), and f
o
Main (TRI-STATE ID
IN
Main pins are all
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in
o