LMX2377UTM National Semiconductor, LMX2377UTM Datasheet - Page 40

• Manufacturer Part Number: LMX2377UTM
• Description: IC FREQ SYNTH DUAL 20TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2377UTM

• Pll: Yes with Bypass
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 2.5GHz, 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 2.5GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LMX2377UTM

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Main
Reg. Most Significant Bit
Divide
N
Ratio
8191
2.0 Programming Description
2.7 MAIN N REGISTER
The Main N register contains the Main N_CNTRA, Main N_CNTRB, PRE Main, and PWDN Main control words. The Main
N_CNTRA and Main N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and
programming information for each control word is discussed in the following sections.
2.7.1 Main N_CNTRA[4:0]
The Main N_CNTRA control word is used to setup the Main synthesizer’s A counter. The A counter is a 5-bit swallow counter used
in the programmable feedback divider. The Main N_CNTRA control word can be programmed to values ranging from 0 to 31.
2.7.2 Main N_CNTRB[12:0] MAIN SYNTHESIZER PROGRAMMABLE BINARY COUNTER (B COUNTER)
Main N[7:19]
The Main N_CNTRB control word is used to setup the Main synthesizer’s B counter. The B counter is a 13-bit programmable
binary counter used in the programmable feedback divider. The Main N_CNTRB control word can be programmed to values
ranging from 3 to 8191.
2.7.3 PRE Main
The Main synthesizer utilizes a selectable dual modulus prescaler.
2.7.4 PWDN Main
The PWDN Main bit is used to switch the Main PLL between a powered up and powered down mode.
Furthermore, the PWDN Main bit operates in conjuction with the TRI-STATE ID
asynchronous powerdown mode.
3
4
•
Divide Ratio
PWDN
Main
PWDN Main
21
Control Bit
Control Bit
PRE Main
31
0
1
•
Main
PRE
20
12
0
0
1
•
19
11
0
0
1
•
18
Register Location
Register Location
17
10
4
0
0
1
MAIN SYNTHESIZER PRESCALER SELECT
MAIN SYNTHESIZER POWERDOWN
•
0
0
1
•
Main N[20]
Main N[21]
MAIN SYNTHESIZER SWALLOW COUNTER (A COUNTER)
16
9
0
0
1
15
•
Main N_CNTRB[12:0]
14
8
0
0
1
•
13
SHIFT REGISTER BIT LOCATION
3
0
0
1
(Continued)
•
Main Prescaler
Select
Main Powerdown
Data Field
12
Main N_CNTRB[12:0]
Description
Description
7
0
0
1
•
11
40
Main N_CNTRA[4:0]
6
0
0
1
•
10
2
0
0
1
•
9
5
0
0
1
•
16/17 Prescaler
Selected
Main PLL Active
8
o
7
4
0
0
1
•
Main bit to set a synchronous or an
0
0
6
Main N_CNTRA[4:0]
3
0
0
1
1
0
0
1
•
•
5
Function
Function
4
2
0
1
1
•
32/33 Prescaler
Selected
Main PLL
Powerdown
Least Significant Bit
3
Main N[21]
Main N[20]
Main N[2:6]
2
1
1
0
1
•
1
1
0
0
1
1
•
Address
1
1
Field
0
1
0
1
•
0
1