SI5318-F-BC Silicon Laboratories Inc, SI5318-F-BC Datasheet - Page 6

• Manufacturer Part Number: SI5318-F-BC
• Description: IC MULTIPLIER SONET/SDH 63CBGA
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5318-F-BC

• Package / Case: 63-CBGA
• Pll: Yes
• Input: LVTTL
• Output: LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 173MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 173MHz
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1180

Si5318
Table 2. DC Characteristics, V
(V
6
Parameter
Supply Current
Power Dissipation Using 3.3 V Supply
Common Mode Input Voltage
(CLKIN)
Single-Ended Input Voltage
(CLKIN)
Differential Input Voltage Swing
(CLKIN)
Input Impedance
(CLKIN+, CLKIN–)
Differential Output Voltage Swing
(CLKOUT)
Output Common Mode Voltage
(CLKOUT)
Output Short to GND (CLKOUT)
Output Short to V
Input Voltage Low (LVTTL Inputs)
Input Voltage High (LVTTL Inputs)
Input Low Current (LVTTL Inputs)
Input High Current (LVTTL Inputs)
Internal Pulldowns (All LVTTL Inputs)
Input Impedance (LVTTL Inputs)
Output Voltage Low (LVTTL Outputs)
Output Voltage High (LVTTL Outputs)
Notes:
DD33
1. The Si5318 device provides weak 1.5 V internal biasing that enables ac-coupled operation.
2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac
3. Transmission line termination, when required, must be provided externally.
4. Although the Si5318 device can operate with input clock swings as high as 1500 mV
= 3.3 V ±5%, T
coupled to ground.
maintaining the input clock amplitude below 500 mV
DD25
A
= –20 to 85 °C)
(CLKOUT)
2,3,4
1,2,3
2,3,4
DD
= 3.3 V
Symbol
V
I
I
V
V
SC(–)
SC(+)
V
V
I
V
R
V
R
V
V
P
OCM
I
I
DD
I
ICM
pd
OD
IH
OH
IL
OL
IS
ID
IN
IH
IN
IL
D
PP
Clock out = 155.52 MHz
Clock out = 155.52 MHz
Clock in = 19.44 MHz
Clock in = 19.44 MHz
Rev. 1.0
for optimal performance.
Test Condition
See Figure 1A
See Figure 1B
Line-to-Line
Line-to-Line
100 Ω Load
100 Ω Load
I
I
O
O
= .5 mA
= .5 mA
PP
Min
200
200
720
–60
1.0
1.4
2.0
2.0
, Silicon Laboratories recommends
50
—
—
—
—
—
—
—
—
—
Typ
135
445
938
1.5
1.8
80
15
—
—
—
—
—
—
—
—
—
—
—
500
500
1155
Max
145
479
2.0
2.2
0.8
0.4
50
50
50
—
—
—
—
—
—
4
4
mV
mV
mV
Unit
mW
mA
mA
mA
k Ω
µA
µA
µA
k Ω
V
V
V
V
V
V
PP
PP
PP