SI5318-G-BC Silicon Laboratories Inc, SI5318-G-BC Datasheet
SI5318-G-BC
Specifications of SI5318-G-BC
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SI5318-G-BC Summary of contents
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... SONET/SDH line/port cards Optical modules Description The Si5318 is a precision clock multiplier designed to exceed the requirements of high-speed communication systems, including OC-48. The device phase locks to an input clock in the 19, 39, 78, or 155 MHz frequency range and generates a low jitter output clock in the 19 or 155 MHz range. Silicon Laboratories’ DSPLL® ...
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... Si5318 N : OTES 2 Rev. 1.0 ...
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... Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3. Pin Descriptions: Si5318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6. 9x9 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Rev ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5318 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient temperature of –20 to 85° C. ...
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... CLKIN+ CLKIN– A. Operation with Single-Ended Clock Input Note: When using single-ended clock sources, the unused clock input on the Si5318 must be ac-coupled to ground. CLKIN+ CLKIN– (CLKIN+) – (CLKIN–) B. Operation with Differential Clock Input Note: Transmission line termination, when required, must be provided Figure 1 ...
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... Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac coupled to ground. 3. Transmission line termination, when required, must be provided externally. 4. Although the Si5318 device can operate with input clock swings as high as 1500 mV maintaining the input clock amplitude below 500 ...
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... CLKIN for Detecting a LOS Condition. INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 Recovery Time for Clearing an LOS Condition VALTIME = 0 VALTIME = 1 *Note: The Si5318 provides a 1/8, 1/4, 1/ clock frequency multiplication function. Symbol Test Condition f CLKIN t Figure Figure ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5318 (tPT_MTIE) never reaches one nanosecond. 8 Symbol ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5318 (tPT_MTIE) never reaches one nanosecond. Symbol Test Condition ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5318 (tPT_MTIE) never reaches one nanosecond. 10 Symbol ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5318 (tPT_MTIE) never reaches one nanosecond. Symbol Test Condition ...
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... Parameter Thermal Resistance Junction to Ambient 0.00 -20.00 -40.00 -60.00 -80.00 -100.00 -120.00 -140.00 -160.00 -180. Figure 4. Typical Si5318 Phase Noise (CLKIN = 155.52 MHz, CLKOUT = 155.52 MHz, and 12 Symbol V –0.5 to 3.6 DD33 V –0 DIG T –55 to 150 JCT T –55 to 150 STG Symbol Test Condition θ ...
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... Input Clock Source 0.1 µF Input Clock Frequency Select (19, 38, 77, or 155 MHz) PLL Bandwidth Select Bandwidth Doubling Fixed Delay Mode Control LOS Validation Time Reset/Calibration Control Figure 5. Si5318 Typical Application Circuit (3.3 V Supply) 2200 kΩ 1% CLKIN+ CLKIN- Si5318 INFRQSEL[2:0] BWSEL[1:0] ...
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... RMS must also drive FXDDELAY high for proper operation. 2.2. Clock Input and Output Rate Selection The Si5318 provides a 1/8x, 1/4x, 1/2x, 1x, 2x, 4x clock frequency multiplication function. Output rates vary in accordance with the input clock rate. The multiplication factor is configured by selecting the input and output clock frequency ranges for the device ...
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... FRQSEL1 Range Reserved 155 MHz 19 MHz Driver Powerdown 2.3. PLL Performance The Si5318 PLL is designed to provide extremely low jitter generation, high jitter tolerance, and a well- * controlled jitter transfer function with low peaking and a DBLBW high degree of jitter attenuation. 1 2.3.1. Jitter Generation ...
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... The frequency accuracy specifications for digital hold mode are given in Table 4 on page 8. 2.5. Hitless Recovery from Digital Hold When the Si5318 device is locked to a valid input clock, a loss of the input clock causes the device to automatically switch to digital hold mode. When the input clock signal returns, the device performs a “ ...
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... Bias Generation Circuitry The Si5318 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption and variation as compared with traditional implementations that use an internal resistor. The bias generation circuitry requires Ω ...
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... Figure 10. Power Supply Noise Tolerance Mask 18 To get optimal performance from the Si5318 device, the power supply noise spectrum must comply with the plot DD25 in Figure 10. This plot shows the power supply noise tolerance mask for the Si5318. The customer should provide a 3 ...
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... Design and Layout Guidelines Precision clock circuits are susceptible to board noise and EMI. To take precautions against unacceptable levels of board noise and EMI affecting performance of the Si5318, consider the following: Power the device from 3.3 V since the internal regulator provides at least isolation to the V pins (which power the PLL circuitry) ...
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... Pin Descriptions: Si5318 8 7 RSVD_NC RSVD_NC RSVD_NC RSVD_GND RSVD_GND RSVD_GND GND DH_ACTV VDD25 CAL_ACTV VDD25 LOS VDD25 GND GND FRQSEL[1] CLKOUT– Figure 11. Si5318 Pin Configuration (Bottom View RSVD_NC RSVD_NC RSVD_NC RSVD_GND RSVD_NC FXDDELAY RSVD_GND GND GND GND GND VDD25 VDD33 VDD33 ...
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... GND D CLKIN+ DBLBW VDD33 E CLKIN– GND VDD33 F INFRQSEL[0] GND VDD25 G INFRQSEL[1] GND GND H INFRQSEL[2] REXT RSTN/CAL Figure 12. Si5318 Pin Configuration (Transparent Top View RSVD_NC RSVD_NC RSVD_NC RSVD_NC FXDDELAY RSVD_NC RSVD_GND RSVD_GND GND GND GND GND VDD33 VDD33 VDD25 VDD25 VDD33 ...
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... Pin Name B4 FXDDELAY D1 CLKIN+ E1 CLKIN– *Note: The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source. 22 Table 10. Si5318 Pin Descriptions I/O Signal Level I* LVTTL Fixed Delay Mode ...
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... INFRQSEL[2] F8 LOS D8 DH_ACTV H3 RSTN/CAL *Note: The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source. I/O Signal Level I* LVTTL Input Frequency Range Select. Pins(INFRQSEL[2:0]) select the frequency range for the input clock, CLKIN ...
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... E8 CAL_ACTV H4 VALTIME A2, A3, B2, RSVD_GND B3, B6, B7, C8 *Note: The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source. 24 I/O Signal Level O CML Differential Clock Output. High frequency clock output. The frequency of the CLKOUT output is a multiple of the frequency of the CLKIN input ...
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... GND GND F2, G2–G8 H2 REXT D2 DBLBW *Note: The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source. I/O Signal Level — LVTTL Reserved—No Connect. ...
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... Si5318 4. Ordering Guide Part Number Si5318-X-BC Note: “X” denotes product revision. 26 Package Temperature 63-Ball CBGA – °C Rev. 1.0 ...
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... Package Outline Figure 13 illustrates the package details for the Si5318. Table 11 lists the values for the dimensions shown in the illustration. Figure 13. 63-Ball Ceramic Ball Grid Array (CBGA) Table 11. Package Drawing Dimensions Dimension Description A Total Package Height A1 A2 Ceramic Thickness A3 Mold Cap Thickness ...
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... Si5318 6. 9x9 mm CBGA Card Layout Placement Courtyard Table 12. Recommended Land Pattern Dimensions Symbol Parameter C Column Width D Row Height E Pad Pitch F Placement Courtyard X Pad Diameter Notes: 1. The Placement Courtyard is the minimum keep-out area required to assure assembly clearances. 2. Pad Diameter is Copper Defined (Non-Solder Mask Defined/NSMD). ...
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... OCUMENT HANGE IST Revision 0.9 to Revision 1.0 Updated θ in Table 6, “Thermal Characteristics,” on page 12. JA Rev. 1.0 Si5318 29 ...
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... Si5318 C I ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...